Patents by Inventor An-Nong Wen

An-Nong Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973048
    Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: April 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: An-Nong Wen, Ching-Han Huang, Ching-Ho Chang
  • Publication number: 20220068868
    Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.
    Type: Application
    Filed: November 8, 2021
    Publication date: March 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Nong WEN, Ching-Han HUANG, Ching-Ho CHANG
  • Patent number: 11171108
    Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 9, 2021
    Inventors: An-Nong Wen, Ching-Han Huang, Ching-Ho Chang
  • Patent number: 11133278
    Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, a cap layer, a conductive terminal, and a dam structure. The semiconductor die has a first surface. The cap layer is over the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminal penetrates the cap layer and electrically connects to the semiconductor die. The dam structure is between the semiconductor die and the cap layer and surrounds a portion of the conductive terminal between the first surface and the second surface, thereby forming a gap between the cap layer and the semiconductor die.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: September 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Che Huang, Ching-Han Huang, An-Nong Wen, Po-Ming Huang
  • Publication number: 20200111761
    Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.
    Type: Application
    Filed: October 3, 2019
    Publication date: April 9, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Nong WEN, Ching-Han HUANG, Ching-Ho CHANG
  • Publication number: 20200111760
    Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, a cap layer, a conductive terminal, and a dam structure. The semiconductor die has a first surface. The cap layer is over the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminal penetrates the cap layer and electrically connects to the semiconductor die. The dam structure is between the semiconductor die and the cap layer and surrounds a portion of the conductive terminal between the first surface and the second surface, thereby forming a gap between the cap layer and the semiconductor die.
    Type: Application
    Filed: September 25, 2019
    Publication date: April 9, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Che HUANG, Ching-Han HUANG, An-Nong WEN, Po-Ming HUANG
  • Patent number: 8048694
    Abstract: A package base structure of a light emitting device and associated manufacturing method is provided. The method includes steps of forming a first mask layer and a second mask layer on a first surface and a second surface of a substrate; defining a first opening and a second opening on the first mask layer and the second mask layer wherein the first opening is larger than the second opening; etching the substrate to form the package base structure having a holding space and at least two through holes. The upper opening of the holding space is located on the first surface of the substrate, and the bottom of the holding space can support the light emitting device. The lower openings of the through holes are located on the second surface of the substrate, and the tops of the through holes reach the bottom of the holding space. There is at least one slant structure at the contact between sidewalls of the through holes and the bottom of the holding space.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: November 1, 2011
    Assignee: Silicon Base Development Inc.
    Inventors: An-Nong Wen, Ching-Chi Cheng, Chih-Ming Chen
  • Publication number: 20110049554
    Abstract: A package base structure for packaging a light-emitting element and a related manufacturing process are provided. The package base structure includes a semiconductor substrate having a top surface, a receiving space in the top surface and defined by slant surfaces, and a micro diffractive optical element on one of the slant surfaces. To produce the package base structure, a first etching mask with a first etching window is formed on the top surface. The etching window has a sidewall oriented at a bias angle with respect to a specific equivalent crystallographic orientation of the semiconductor substrate. Then, a selective anisotropic etching procedure is performed through the first etching window to form the slant surfaces on the semiconductor substrate. Afterwards, the micro diffractive optical element is formed on the slant surface for collimating or focusing a light beam emitted from the light-emitting element.
    Type: Application
    Filed: August 27, 2010
    Publication date: March 3, 2011
    Applicant: NATIONAL CENTRAL UNIVERSITY
    Inventors: Mao-Jen Wu, Hsiao-Chin Lan, An-Nong Wen, Chih-Hung Hsu, Hsu-Liang Hsiao, Chia-Chi Chang, Chia-Yu Lee, Siou-Ping Chen, Min-Hao Chung
  • Publication number: 20100220575
    Abstract: An optical pickup head includes a first light source, a second light source, a base, a light adjusting unit, and a light guiding unit. The first light source emits a first wavelength light beam to read a first data density optical storage medium. The second light source emits a second wavelength light beam to read a second data density optical storage medium. The base includes at least a slant surface for reflecting the first wavelength light beam and the second wavelength light beam, so that the first wavelength light beam and the second wavelength light beam are parallel with each other. The light adjusting unit adjusts the first wavelength light beam and the second wavelength light beam to the same optical axis. The light guiding unit guides the first wavelength light beam and the second wavelength light beam to the first data density optical storage medium or the second data density optical storage medium.
    Type: Application
    Filed: February 26, 2010
    Publication date: September 2, 2010
    Applicant: NATIONAL CENTRAL UNIVERSITY
    Inventors: Wen-Hsin Sun, Mao-Jen Wu, Hsiao-Chin Lan, An-Nong Wen, Chih-Hung Hsu
  • Patent number: 7701050
    Abstract: A side-view optical diode package is mounted on a printed circuit board with at least a solder bump. The side-view optical diode package includes a silicon substrate, a holding space, a bonding surface and a positioning structure. The silicon substrate has a first surface and a second surface. The holding space has a top opening in the first surface and a bottom for holding an optical diode thereon. The bonding surface is disposed at a lateral side of the silicon substrate and bonded onto the printed circuit board. The positioning structure has at least a solder-receiving portion beside the bonding surface and corresponding to the solder bump. The solder bump is molten during a soldering process and received in the solder-receiving portion, thereby facilitating positioning the silicon substrate on the printed circuit board.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: April 20, 2010
    Assignee: Silicon Base Development Inc.
    Inventors: Chih-Ming Chen, Deng-Huei Hwang, Ching-Chi Cheng, An-Nong Wen
  • Publication number: 20080142832
    Abstract: A side-view optical diode package is mounted on a printed circuit board with at least a solder bump. The side-view optical diode package includes a silicon substrate, a holding space, a bonding surface and a positioning structure. The silicon substrate has a first surface and a second surface. The holding space has a top opening in the first surface and a bottom for holding an optical diode thereon. The bonding surface is disposed at a lateral side of the silicon substrate and bonded onto the printed circuit board. The positioning structure has at least a solder-receiving portion beside the bonding surface and corresponding to the solder bump. The solder bump is molten during a soldering process and received in the solder-receiving portion, thereby facilitating positioning the silicon substrate on the printed circuit board.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 19, 2008
    Applicant: SILICON BASE DEVELOPMENT INC.
    Inventors: Chih-Ming Chen, Deng-Huei Hwang, Ching-Chi Cheng, An-Nong Wen
  • Publication number: 20080036045
    Abstract: A process of manufacturing a package base of a power semiconductor device includes the following steps. Firstly, a semiconductor substrate including a first surface and a second surface is provided. Then, a portion of the semiconductor substrate is patterned and removed to form a recess on the first surface of the semiconductor substrate, which serves as a receiving space for receiving a power semiconductor element therein. Then, a conducting layer is overlaid on the first surface including the receiving space. Afterward, a portion of the conducting layer is patterned and removed to form a conducting structure to be electrically connected to the power semiconductor device.
    Type: Application
    Filed: August 8, 2007
    Publication date: February 14, 2008
    Applicant: SILICON BASE DEVELOPMENT INC.
    Inventors: Chih-Ming Chen, Ching-Chi Cheng, An-Nong Wen
  • Publication number: 20070246724
    Abstract: A package base structure of a light emitting device and associated manufacturing method is provided. The method includes steps of forming a first mask layer and a second mask layer on a first surface and a second surface of a substrate; defining a first opening and a second opening on the first mask layer and the second mask layer wherein the first opening is larger than the second opening; etching the substrate to form the package base structure having a holding space and at least two through holes. The upper opening of the holding space is located on the first surface of the substrate, and the bottom of the holding space can support the light emitting device. The lower openings of the through holes are located on the second surface of the substrate, and the tops of the through holes reach the bottom of the holding space. There is at least one slant structure at the contact between sidewalls of the through holes and the bottom of the holding space.
    Type: Application
    Filed: April 2, 2007
    Publication date: October 25, 2007
    Applicant: Silicon Base Development Inc.
    Inventors: An-Nong Wen, Ching-Chi Cheng, Chih-Ming Chen