Patents by Inventor An-Pin Wang

An-Pin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11211301
    Abstract: A semiconductor device includes a first conductive feature and a second conductive feature. A first passivation layer is positioned between the first conductive feature and the second conductive feature. A second passivation layer is positioned between the first conductive feature and the second conductive feature and over the first passivation layer. A lowermost portion of an interface where the first passivation layer contacts the second passivation layer is positioned below 40% or above 60% of a height of the first conductive feature.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chunting Wu, Ching-Hou Su, Chih-Pin Wang
  • Publication number: 20210369776
    Abstract: The present disclosure is directed towards genetically engineered TCR-T cells to recognize tumor antigens and simultaneously secrete a binding protein that blocks an immune checkpoint molecule and TGF-beta. These engineered T cells demonstrate stronger antitumor response and reduced T cell exhaustion. The present disclosure provides immunotherapy against HPV- or EBV-positive cancers, among others.
    Type: Application
    Filed: December 5, 2019
    Publication date: December 2, 2021
    Inventors: Si Li, Pin Wang, Paul Bryson, Peter Alexander, Rui Chen
  • Patent number: 11191175
    Abstract: An electronic apparatus has a rear cover and a mount assembly coupled to the rear cover. The mount assembly has a first kit coupled to the rear cover and a second kit removably coupled to the first kit. The first kit has a first mount bracket and a kit rib. The second kit has a second mount bracket corresponding to the first mount bracket and an installation corresponding to the kit rib. When the first kit is rotated relative to the second kit, the rotation of the first kit is restricted by a rib assembly between the kit rib and the installation.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: November 30, 2021
    Assignees: ShenZhen Hongfei Precision Technology Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wen-Pin Wang, Li-Wei Chen, Hsueh-Ho Han
  • Publication number: 20210343587
    Abstract: An integrated circuit (IC) structure includes a substrate, a transistor, an interconnect structure, a plurality of metal lines, an oxide liner, a passivation layer, and a nitride layer. The transistor is on the substrate. The interconnect structure is over the transistor. The metal lines is on the interconnect structure. The oxide liner is over the plurality of metal lines. The passivation layer is over the oxide liner and is more porous than the passivation layer. The nitride layer is over the passivation layer.
    Type: Application
    Filed: July 16, 2021
    Publication date: November 4, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chiang CHEN, Chun-Ting WU, Ching-Hou SU, Chih-Pin WANG
  • Patent number: 11105686
    Abstract: Due to potential sampling errors (due to small tissue samples not necessarily directly from the developing tumor) and limited optical resolution (˜1 micron), cancer may be missed or detected too late for optimal treatment, or conservative interpretation of indeterminate findings could lead to unnecessary surgery. The novel technology herein—Spatial-domain Low-coherence Quantitative Phase Microscopy (SL-QPM)—can detect structural alterations within cell nuclei with nanoscale sensitivity (0.9 nm) (or nuclear nano-morphology) for “nano-pathological diagnosis” of cancer. SL-QPM uses original, unmodified cytology and histology specimens prepared with standard clinical protocols and stains. SL-QPM can easily integrate in existing clinical pathology laboratories. Results quantified the spatial distribution of optical path length or refractive index in individual nuclei with nanoscale sensitivity, which could be applied to studying nuclear nano-morphology as cancer progresses.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: August 31, 2021
    Assignee: University of Pittshurgh-Of the Commonwealth System of Higher Education
    Inventors: Yang Liu, Randall E. Brand, Pin Wang, Shikhar Fnu
  • Publication number: 20210267078
    Abstract: A device stand for supporting an electronic panel that is covered by a rear panel includes a first stand surface and a second stand surface that intersects the first stand surface. A plurality of first stand holes in a first hole group is located on the first stand surface and a plurality of second stand holes in a second hole group is located on the second stand surface. The device stand is removably coupled to the rear panel through the plurality of first stand holes when the electronic panel is disposed on a first plane and is removably coupled to the rear panel through the plurality of second stand holes when the electronic panel is mounted on a second plane different from the first plane.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 26, 2021
    Inventors: WEN-PIN WANG, LI-WEI CHEN, HSUEH-HO HAN
  • Publication number: 20210249321
    Abstract: A semiconductor device includes a first conductive feature and a second conductive feature. A first passivation layer is positioned between the first conductive feature and the second conductive feature. A second passivation layer is positioned between the first conductive feature and the second conductive feature and over the first passivation layer. A lowermost portion of an interface where the first passivation layer contacts the second passivation layer is positioned below 40% or above 60% of a height of the first conductive feature.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 12, 2021
    Inventors: Chunting WU, Ching-Hou SU, Chih-Pin WANG
  • Patent number: 11068369
    Abstract: A test method for a basic input/output system (BIOS), configured to test a computer device which includes the BIOS when a power on self test (POST) of the BIOS fails, is disclosed including following operations: enabling a fixing function of the BIOS by a debug port of a motherboard of the computer device; enabling a first memory device and disabling a second memory device, by the debug port; according to the fixing function, turning on the computer device by the first memory device; and determining whether the computer device is turned on successfully.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 20, 2021
    Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATION
    Inventor: Tzu-Pin Wang
  • Patent number: 11069562
    Abstract: A method includes forming metal lines over an interconnect structure that is formed above transistors; depositing a liner layer over the metal lines using a first high density plasma chemical vapor deposition (HDPCVD) process with a zero RF bias power depositing a first passivation layer over the liner layer using a second HDPCVD process with a non-zero RF bias power; and depositing a second passivation layer in contact with a top surface of the first passivation layer using a third HDPCVD process with a non-zero RF bias power.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chiang Chen, Chun-Ting Wu, Ching-Hou Su, Chih-Pin Wang
  • Publication number: 20210217659
    Abstract: A method includes forming metal lines over an interconnect structure that is formed above transistors; depositing a liner layer over the metal lines using a first high density plasma chemical vapor deposition (HDPCVD) process with a zero RF bias power depositing a first passivation layer over the liner layer using a second HDPCVD process with a non-zero RF bias power; and depositing a second passivation layer in contact with a top surface of the first passivation layer using a third HDPCVD process with a non-zero RF bias power.
    Type: Application
    Filed: January 15, 2020
    Publication date: July 15, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chiang CHEN, Chun-Ting WU, Ching-Hou SU, Chih-Pin WANG
  • Publication number: 20210123516
    Abstract: A low-noise lifting device includes a rack and a gear. The rack includes first teeth each having a first crown portion. A surface of the first crown portion is defined as a first contact surface having a circular arc shape. The gear includes second teeth. A second root portion is defined between every adjacent two of the second teeth. A surface of the second root portion is defined as a second contact surface having a circular arc shape. When the gear is meshed with the rack, the second contact surface and the first contact surface are in close contact with each other in a circular arc shape, without a backlash, so as to reduce the noise generated by the transmission.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 29, 2021
    Inventor: WEN-PIN WANG
  • Publication number: 20210095029
    Abstract: Described herein are compositions a genetically modified comprising nucleic acids encoding a chimeric antigen receptor (CAR) and a checkpoint inhibitor and methods for using the compositions to treat cancer.
    Type: Application
    Filed: April 19, 2018
    Publication date: April 1, 2021
    Applicant: University of Southern California
    Inventors: Pin WANG, Natnaree SIRIWON, Si LI
  • Patent number: 10877283
    Abstract: The present invention provides a light source module. The first light source forms the first beam from the second light source, the third light source, and the function of the first beam splitter. Then the second beam splitter reflects the first beam and transmits the fourth beam from the fourth light source for forming the mixed beam, which is received and projected by the optical processing device. Thereby, by using the high color rendering and special optical properties of the mixed beam, the applications and efficacy of the present invention can be improved.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: December 29, 2020
    Assignee: T.Q. Optoelectronics Co., Ltd.
    Inventors: Huan-Ping Chiu, Ji-Pin Wang, Juergen Mueller, Gerald Uhlenberg
  • Publication number: 20200379859
    Abstract: A test method for a basic input/output system (BIOS), configured to test a computer device which includes the BIOS when a power on self test (POST) of the BIOS fails, is disclosed including following operations: enabling a fixing function of the BIOS by a debug port of a motherboard of the computer device; enabling a first memory device and disabling a second memory device, by the debug port; according to the fixing function, turning on the computer device by the first memory device; and determining whether the computer device is turned on successfully.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 3, 2020
    Inventor: Tzu-Pin WANG
  • Patent number: 10849426
    Abstract: The present disclosure provides a rear structure coupled to a display panel. The rear structure comprises a rear cover comprising a rib structure for supporting the display panel, the rib structure comprising a plurality of horizontal bars, a plurality of vertical bars, and a plurality of blocks, and each of the blocks formed by at least one of the horizontal bars and at least one of the vertical bars. Wherein a first section of the rib structure comprises at least two aligned adjacent horizontal bars and at least two aligned adjacent vertical bars, and a second section of the rib structure comprises at least two non-aligned vertical bars.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: December 1, 2020
    Assignees: ShenZhen Hongfei Precision Technology Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wen-Pin Wang, Yao-Shih Chung, I-Ting Huang, Yu-Jen Chang, Hai-Ping Xiang, Hui Huang, Xiu-Gao Yang, Dong-Ping Zhang, Yong Yang, Hui Zhang, Bo Hu, Qin Sun
  • Patent number: 10822419
    Abstract: The invention is directed to a masked chimeric antigen receptor, comprising: (a) a masking peptide; (b) one or more antigen-specific targeting domains; (c) an extracellular spacer domain; (d) a transmembrane domain; (e) at least one co-stimulatory domain; and (f) an intracellular signaling domain. The mCARs are activated upon cleavage of the masking peptide.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: November 3, 2020
    Assignee: University of Southern California
    Inventors: Pin Wang, Xiaolu Han, Paul Bryson
  • Patent number: 10811115
    Abstract: A test method for testing a built-in memory in a computer device includes the following operations. The built-in memory is tested by a test function of a basic input/output system (BIOS) in the computer device to create a data file. An analysis application is performed by a test device to analyze the data file. According to analyzing the data file, an abnormal memory chip is determined whether to exist in the built-in memory. The data file includes test data of memory chips in the built-in memory.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: October 20, 2020
    Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATION
    Inventors: Tzu-Pin Wang, Kuo-Hsin Hsu, I-Ting Liu, Che-Sheng Cheng
  • Publication number: 20200302858
    Abstract: A conductive substrate of a display device has an electrically insulating substrate and a plurality of rows of electrical pin connecting areas, a plurality of rows of patterned input voltage lines and a plurality of rows of patterned grounded lines formed on the electrically insulated substrate. Each of the rows of the electrical pin connecting areas includes a plurality of electrical pin connecting areas electrically isolated and spaced from each other in a line. The rows of the patterned input voltage lines are respectively adjacent to the rows of the electrical pin connecting areas, and the rows of the patterned grounded lines are respectively adjacent to the rows of the electrical pin connecting areas.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 24, 2020
    Inventors: WEN-CHANG FAN, CHIA-PIN WANG, BO-SHENG LU
  • Publication number: 20200295864
    Abstract: An iterative detection and decoding (IDD) circuit is provided. The iterative detection and decoding (IDD) circuit is configured to perform M outer iterations on a received signal, and Ni inner iterations are performed during the ith outer iteration of the M outer iterations, where M is an integer greater than 1, i is an integer less than or equal to M, and N1 to NM are integers and include at least two different values.
    Type: Application
    Filed: June 28, 2019
    Publication date: September 17, 2020
    Inventors: Chia-Hsiang YANG, Yao-Pin Wang, Chi-Chih Wen, Der-Zheng Liu, Chung-Jung Huang
  • Patent number: 10716402
    Abstract: The present disclosure provides a rear structure coupled to a display panel. The rear structure comprises a wall mount assembly comprising a first kit comprising a first wall mount bracket, a plurality of circularly arranged first trenches, and a plurality of first magnets accommodated by the first trenches, and a second kit removably coupled to the first kit comprising a second wall mount bracket structurally complementary to the first wall mount bracket, a plurality of circularly arranged second trenches, and a plurality of second magnets accommodated by the second trenches. Wherein when the first kit is coupled to the second kit, each of the first magnets is located corresponds to one of the second magnets, and a magnetism of a side of one of the first magnets facing the second kit is opposite to a magnetism of a side of one of the second magnets facing the first kit.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: July 21, 2020
    Assignees: ShenZhen Hongfei Precision Technology Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wen-Pin Wang, Yao-Shih Chung, Shih-Hong Fu