Abstract: The semiconductor structure includes a die, a dielectric layer surrounding the die, a photoelectric device disposed adjacent to the die and surrounded by the dielectric layer, a first opening extending through the redistribution layer and configured to receive a light-conducting member, and a metallic shield extending at least partially through the redistribution layer and surrounding the first opening. A method for forming a semiconductor structure includes receiving a die; forming a dielectric layer to surround the die; and disposing a photoelectric device surrounded by the dielectric layer; forming a redistribution layer over the die, the dielectric layer and the photoelectric device; and removing a portion of the redistribution layer to form a first opening over the photoelectric device. A metallic shield extending at least partially through the redistribution layer and surrounding the first opening is formed during the formation of the redistribution layer.

Abstract: An electronic device, applicable to a V2X system is disclosed. The electronic device includes a wireless transceiver and a processor. The wireless transceiver is configured to receive a first collective perception message from another device of the V2X system. The processor is coupled to the wireless transceiver, and the processor is configured to operate the following operations: determining whether to generate a second collective perception message according to the first collective perception message according to a first angle of the electronic device and a second angle of another device of the first collective perception message; and sending the second collective perception message to several surrounding devices surrounding the electronic device through the wireless transceiver.

Abstract: A photosensitive device is provided. The photosensitive device includes a sensing stack, an anti-reflective layer, an optical filter, a first electrode, and a second electrode. The sensing stack includes a first semiconductor layer, an intrinsic semiconductor layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the intrinsic semiconductor layer. The anti-reflective layer is disposed on a side of the sensing stack. The optical filter is disposed on the anti-reflective layer and blocks input light with an incident angle greater than 50 degrees. The first electrode and the second electrode are disposed on the sensing stack.

Abstract: A method includes applying a first voltage to a source of a first transistor of a detector unit of a semiconductor detector in a test wafer and applying a second voltage to a gate of the first transistor and a drain of a second transistor of the detector unit. The first transistor is coupled to the second transistor in series, and the first voltage is higher than the second voltage. A pre-exposure reading operation is performed to the detector unit. Light of an exposure apparatus is illuminated to a gate of the second transistor after applying the first and second voltages. A post-exposure reading operation is performed to the detector unit. Data of the pre-exposure reading operation is compared with the post-exposure reading operation. An intensity of the light is adjusted based on the compared data of the pre-exposure reading operation and the post-exposure reading operation.

Abstract: A semiconductor package includes a first connection die including a semiconductor substrate and an interconnect structure, and a first die stack disposed on the first connection die and including stacked dies, each of the stacked dies including a semiconductor substrate and an interconnect structure including a first connection line that is electrically connected to the interconnect structure of the first connection die. An angle formed between a plane of the first connection die and a plane of each stacked die ranges from about 45° to about 90°.

Abstract: A deep trench capacitor includes at least one deep trench and a layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers and continuously extending over the top surface of a substrate and into each of the at least one deep trench. A contact-level dielectric layer overlies the substrate and the layer stack. Contact assemblies extend through the contact-level dielectric layer. A subset of the contact assemblies vertically extend through a respective metallic electrode layer. For example, a first contact assembly includes a first tubular insulating spacer that laterally surrounds a first contact via structure and contacts a cylindrical sidewall of a topmost metallic electrode layer.

Abstract: A compound of Formula (I): or a pharmaceutically acceptable salt thereof, in which Ring X is a 3 to 7 membered monocyclic ring, at least one of R1, R2, R3, and R4 is OR5 or CH2OR5 and the other R1, R2, R3, and R4 each independently are halogen, OH, OR5, CH2OR5, CO2H, OC?OR6, (C?O)R6, R6, C1-10 alkyl, C2-10 alkenyl, C2-10 alkynyl, H, or absent. Also provided herein are therapeutic uses of the compound of Formula (I).

Abstract: A retinal layer quantification system includes an image capturing unit and a processor electrically connected to the image capturing unit. The image capturing unit is configured to capture a target optical coherence tomographic image of a subject. The processor stores a program including a target image pre-processing module, a retinal layer auto-segmentation model, a target image enhancement module, a layer thickness detection module and a layer area detection module. The program detects a retinal layer thickness and a retinal layer area of the subject when the program is executed by the processor.

Abstract: Fabricating a photomask includes forming a protection layer over a substrate. A plurality of multilayers of reflecting films are formed over the protection layer. A capping layer is formed over the plurality of multilayers. An absorption layer is formed over capping layer. A first photoresist layer is formed over portions of absorption layer. Portions of the first photoresist layer and absorption layer are patterned, forming first openings in absorption layer. The first openings expose portions of the capping layer. Remaining portions of first photoresist layer are removed and a second photoresist layer is formed over portions of absorption layer. The second photoresist layer covers at least the first openings. Portions of the absorption layer and capping layer and plurality of multilayer of reflecting films not covered by the second photoresist layer are patterned, forming second openings. The second openings expose portions of protection layer and second photoresist layer is removed.

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Abstract: A fault detection method, includes the following steps. A target sequence is received, the target sequence includes several data. A first moving average operation is performed on the target sequence to establish a first moving average sequence. A second moving average operation is performed on the target sequence to establish a second moving average sequence. A difference operation between the first moving average sequence and the second moving average sequence is performed to obtain a difference sequence, the difference sequence includes several difference values. An upper limit value is set. When one of the difference values is greater than the upper limit value, the target sequence is determines as abnormal.

Abstract: A cabinet for receiving an energy storage apparatus includes a substantially cube-shaped frame and a plurality of sheet-shaped concrete structures attached to the frame. The sheet-shaped concrete structure includes an ultra-high performance concrete (UHPC).

Abstract: The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies, and a benchmark circuit disposed on the scribe line. The benchmark circuit includes a first switching circuit, a first process control monitoring (PCM) device and a second PCM device coupled to the first switching circuit, and a second switching circuit. The first switching circuit is configured to selectively couple the first PCM device and the second PCM device to receive a test signal, wherein the first PCM device and the second PCM device are configured to output a first output signal and a second output signal in response to the test signal, respectively. The second switching circuit is configured to selectively couple the first PCM device and the second PCM device to output the first output signal or the second output signal.

Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.

Abstract: A gas deflector contains: a body and a guide unit. The body includes at least one inflow orifice, at least one outflow orifice, and multiple suction orifices. The guide unit includes a support plate, a through orifice, a conduct assembly, a collection assembly including a collecting channel, and a spray orifice. The conduct assembly includes two guiders, a drain orifice extending along the conduct assembly and corresponding to the through orifice and the collecting channel. The collection assembly corresponds to the drain orifice, and the collection assembly includes at least one collector sheet fixed on a bottom of the conduct assembly, and at least one gas conducting element received in the collecting channel. Furthermore, an exhaust channel is defined among the body, the collection assembly and the support plate, and the exhaust channel is in communication with at least one suction orifice of the multiple suction orifices.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.

Abstract: A capacitive biosensor is provided. The capacitive biosensor includes: a transistor, an interconnect structure on the transistor, and a passivation layer on the interconnect structure. The interconnect structure includes a first metal structure on the transistor, a second metal structure on the first metal structure, and a third metal structure on the second metal structure. The third metal structure includes a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked. The passivation has an opening exposing a portion of the third metal structure. The capacitive biosensor further includes a sensing region on the interconnect structure. The sensing region includes a first sensing electrode and a second sensing electrode. The first sensing electrode is formed of the third conductive layer, and the second sensing electrode is disposed on the passivation layer.

Abstract: The present invention provides quaternary ammonium cyclodextrin and a preparation method and uses thereof, as well as a silver nanoparticle-cyclodextrin complex and a preparation method and uses thereof. The quaternary ammonium cyclodextrin of the present invention is introduced with an amine group and quaternary ammonium groups, while retaining the special structure and properties of cyclodextrin itself. The amine group contained in the structure plays a role in reducing and complexing Ag+ in the synthesis of AgNPs, and plays a certain role in stabilizing nanoparticles and forming a complex in combination with quaternary ammonium groups.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: A battery cell including a membrane electrode assembly, a cathode bipolar plate and an anode bipolar plate. The anode bipolar plate includes a metal layer and a thermally conductive layer. The metal layer is stacked on a side of the membrane electrode assembly that is located farthest away from the cathode bipolar plate. The metal layer has a bottom surface, a top surface, a first side surface and a second side surface. The bottom surface faces the membrane electrode assembly. The thermally conductive layer includes a first cover layer and two second cover layers. The first cover layer covers the top surface of the metal layer. The two second cover layers protrude from two opposite sides of the first cover layer, respectively. The two second cover layers at least partially cover the first side surface and the second side surface of the metal layer, respectively.