Patents by Inventor An-Ping CHANG

An-Ping CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240206193
    Abstract: A package structure and a formation method are provided. The method includes bonding a first memory-containing chip structure to a second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. The method also includes bonding a logic control chip structure to the second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. The logic control chip structure is formed using a more advanced technology node than the second memory-containing chip structure.
    Type: Application
    Filed: January 9, 2023
    Publication date: June 20, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang WANG, Tso-Jung CHANG, Wen-Shiang LIAO, Jeng-Shien HSIEH, Chih-Peng LIN, Shih-Ping LIN, Chieh-Yen CHEN, Chen-Hua YU
  • Publication number: 20240203918
    Abstract: A chip stack structure is provided. The chip stack structure includes a first chip including a first substrate and a first interconnect structure over the first substrate. The chip stack structure includes a second chip over and bonded to the first chip. The second chip has a second interconnect structure and a second substrate over the second interconnect structure. The chip stack structure includes an insulating layer over the second interconnect structure and surrounding the second substrate. The chip stack structure includes a conductive plug penetrating through the insulating layer to the second interconnect structure.
    Type: Application
    Filed: January 6, 2023
    Publication date: June 20, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chuei-Tang WANG, Tso-Jung CHANG, Shih-Ping LIN, Jeng-Shien HSIEH, Chih-Peng LIN, Chieh-Yen CHEN, Chen-Hua YU
  • Publication number: 20240198148
    Abstract: The present disclosure provides a movable cabinet and an energy storage apparatus. The movable cabinet includes a concrete main body and a flame retardant material layer. The concrete main body includes a plurality of walls forming an accommodating space. The flame retardant material layer is disposed on one or more inner surfaces of the plurality of walls in the accommodating space.
    Type: Application
    Filed: December 15, 2022
    Publication date: June 20, 2024
    Inventors: An-Ping CHANG, Jong-Peir LI
  • Patent number: 12015010
    Abstract: A semiconductor device includes a first semiconductor die, a second semiconductor die including a side surface bonded to the first semiconductor die, such that the second semiconductor die is perpendicular to the first semiconductor die, and a junction circuit for connecting the first semiconductor die to the second semiconductor die.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jen-Yuan Chang, Chia-Ping Lai
  • Patent number: 12015031
    Abstract: In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Yi Kao, Szu-Ping Lee, Che-Hao Chang, Chun-Heng Chen, Yung-Cheng Lu, Chi On Chui
  • Patent number: 12011430
    Abstract: The present disclosure provides pharmaceutical compositions comprising a cannabinoid, and dosage forms comprising same, for oral delivery, such as sublingual or buccal delivery. The compositions of the present disclosure are substantially homogeneous and remain stable and monophasic upon storage. Also provided are methods of using the compositions for pain management and to treat various diseases and conditions, including dementia, sleep disorders, movement disorders, mental disorders, and multiple sclerosis.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: June 18, 2024
    Assignee: RHODES TECHNOLOGIES
    Inventors: Ping Chang, Marc Brown, Charles Evans
  • Publication number: 20240195446
    Abstract: An electronic device, applicable to a V2X system is disclosed. The electronic device includes a wireless transceiver and a processor. The wireless transceiver is configured to receive a first collective perception message from another device of the V2X system. The processor is coupled to the wireless transceiver, and the processor is configured to operate the following operations: determining whether to generate a second collective perception message according to the first collective perception message according to a first angle of the electronic device and a second angle of another device of the first collective perception message; and sending the second collective perception message to several surrounding devices surrounding the electronic device through the wireless transceiver.
    Type: Application
    Filed: January 19, 2023
    Publication date: June 13, 2024
    Inventor: Ke-Ping CHANG
  • Publication number: 20240188827
    Abstract: A photosensitive device is provided. The photosensitive device includes a sensing stack, an anti-reflective layer, an optical filter, a first electrode, and a second electrode. The sensing stack includes a first semiconductor layer, an intrinsic semiconductor layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the intrinsic semiconductor layer. The anti-reflective layer is disposed on a side of the sensing stack. The optical filter is disposed on the anti-reflective layer and blocks input light with an incident angle greater than 50 degrees. The first electrode and the second electrode are disposed on the sensing stack.
    Type: Application
    Filed: December 11, 2023
    Publication date: June 13, 2024
    Inventors: Pei-Fang TSOU, Yu-Jing FANG, Cheng-Ping CHANG, Yen-Chih CHOU, Chun-Heng LEE, Hsiao Heng HO
  • Publication number: 20240192455
    Abstract: The semiconductor structure includes a die, a dielectric layer surrounding the die, a photoelectric device disposed adjacent to the die and surrounded by the dielectric layer, a first opening extending through the redistribution layer and configured to receive a light-conducting member, and a metallic shield extending at least partially through the redistribution layer and surrounding the first opening. A method for forming a semiconductor structure includes receiving a die; forming a dielectric layer to surround the die; and disposing a photoelectric device surrounded by the dielectric layer; forming a redistribution layer over the die, the dielectric layer and the photoelectric device; and removing a portion of the redistribution layer to form a first opening over the photoelectric device. A metallic shield extending at least partially through the redistribution layer and surrounding the first opening is formed during the formation of the redistribution layer.
    Type: Application
    Filed: February 20, 2024
    Publication date: June 13, 2024
    Inventors: JEN-YUAN CHANG, CHIA-PING LAI
  • Patent number: 12009405
    Abstract: A deep trench capacitor includes at least one deep trench and a layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers and continuously extending over the top surface of a substrate and into each of the at least one deep trench. A contact-level dielectric layer overlies the substrate and the layer stack. Contact assemblies extend through the contact-level dielectric layer. A subset of the contact assemblies vertically extend through a respective metallic electrode layer. For example, a first contact assembly includes a first tubular insulating spacer that laterally surrounds a first contact via structure and contacts a cylindrical sidewall of a topmost metallic electrode layer.
    Type: Grant
    Filed: August 28, 2021
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jen-Yuan Chang, Chia-Ping Lai, Chien-Chang Lee
  • Patent number: 12009349
    Abstract: A semiconductor package includes a first connection die including a semiconductor substrate and an interconnect structure, and a first die stack disposed on the first connection die and including stacked dies, each of the stacked dies including a semiconductor substrate and an interconnect structure including a first connection line that is electrically connected to the interconnect structure of the first connection die. An angle formed between a plane of the first connection die and a plane of each stacked die ranges from about 45° to about 90°.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jen-Yuan Chang, Chia-Ping Lai
  • Patent number: 12009177
    Abstract: A method includes applying a first voltage to a source of a first transistor of a detector unit of a semiconductor detector in a test wafer and applying a second voltage to a gate of the first transistor and a drain of a second transistor of the detector unit. The first transistor is coupled to the second transistor in series, and the first voltage is higher than the second voltage. A pre-exposure reading operation is performed to the detector unit. Light of an exposure apparatus is illuminated to a gate of the second transistor after applying the first and second voltages. A post-exposure reading operation is performed to the detector unit. Data of the pre-exposure reading operation is compared with the post-exposure reading operation. An intensity of the light is adjusted based on the compared data of the pre-exposure reading operation and the post-exposure reading operation.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: June 11, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Ya-Chin King, Chrong-Jung Lin, Burn-Jeng Lin, Chien-Ping Wang, Shao-Hua Wang, Chun-Lin Chang, Li-Jui Chen
  • Publication number: 20240180415
    Abstract: A retinal layer quantification system includes an image capturing unit and a processor electrically connected to the image capturing unit. The image capturing unit is configured to capture a target optical coherence tomographic image of a subject. The processor stores a program including a target image pre-processing module, a retinal layer auto-segmentation model, a target image enhancement module, a layer thickness detection module and a layer area detection module. The program detects a retinal layer thickness and a retinal layer area of the subject when the program is executed by the processor.
    Type: Application
    Filed: June 20, 2023
    Publication date: June 6, 2024
    Inventors: Ching-Ping CHANG, Jia-Yi HONG, Shu-Chun KUO, Jui-Ti MA, Chung-Hsin TSENG
  • Publication number: 20240180945
    Abstract: A compound of Formula (I): or a pharmaceutically acceptable salt thereof, in which Ring X is a 3 to 7 membered monocyclic ring, at least one of R1, R2, R3, and R4 is OR5 or CH2OR5 and the other R1, R2, R3, and R4 each independently are halogen, OH, OR5, CH2OR5, CO2H, OC?OR6, (C?O)R6, R6, C1-10 alkyl, C2-10 alkenyl, C2-10 alkynyl, H, or absent. Also provided herein are therapeutic uses of the compound of Formula (I).
    Type: Application
    Filed: October 24, 2023
    Publication date: June 6, 2024
    Applicant: SyneuRx International (Taiwan) Corp.
    Inventors: Guochuan Emil Tsai, Yi-Wen Mao, Lu-Ping Lu, Wei-Hua Chang, Han-Yi Hsieh, Jhe Wei Hu, Tsai-Miao Shih, ChanHui Huang
  • Patent number: 12001132
    Abstract: Fabricating a photomask includes forming a protection layer over a substrate. A plurality of multilayers of reflecting films are formed over the protection layer. A capping layer is formed over the plurality of multilayers. An absorption layer is formed over capping layer. A first photoresist layer is formed over portions of absorption layer. Portions of the first photoresist layer and absorption layer are patterned, forming first openings in absorption layer. The first openings expose portions of the capping layer. Remaining portions of first photoresist layer are removed and a second photoresist layer is formed over portions of absorption layer. The second photoresist layer covers at least the first openings. Portions of the absorption layer and capping layer and plurality of multilayer of reflecting films not covered by the second photoresist layer are patterned, forming second openings. The second openings expose portions of protection layer and second photoresist layer is removed.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Cheng Hsu, Ta-Cheng Lien, Ping-Hsun Lin, Shih-Che Wang, Hsin-Chang Lee
  • Patent number: 12002774
    Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: June 4, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
  • Publication number: 20240178498
    Abstract: A cabinet for receiving an energy storage apparatus includes a substantially cube-shaped frame and a plurality of sheet-shaped concrete structures attached to the frame. The sheet-shaped concrete structure includes an ultra-high performance concrete (UHPC).
    Type: Application
    Filed: October 17, 2023
    Publication date: May 30, 2024
    Inventor: An-Ping CHANG
  • Publication number: 20240176335
    Abstract: A fault detection method, includes the following steps. A target sequence is received, the target sequence includes several data. A first moving average operation is performed on the target sequence to establish a first moving average sequence. A second moving average operation is performed on the target sequence to establish a second moving average sequence. A difference operation between the first moving average sequence and the second moving average sequence is performed to obtain a difference sequence, the difference sequence includes several difference values. An upper limit value is set. When one of the difference values is greater than the upper limit value, the target sequence is determines as abnormal.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 30, 2024
    Inventors: Yung-Yu Yang, Kang-Ping Li, Chih-Kuan Chang, Chung-Chih Hung, Chen-Hui Huang, Nai-Ying Lo, Shih-Wei Huang
  • Publication number: 20240175920
    Abstract: The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies, and a benchmark circuit disposed on the scribe line. The benchmark circuit includes a first switching circuit, a first process control monitoring (PCM) device and a second PCM device coupled to the first switching circuit, and a second switching circuit. The first switching circuit is configured to selectively couple the first PCM device and the second PCM device to receive a test signal, wherein the first PCM device and the second PCM device are configured to output a first output signal and a second output signal in response to the test signal, respectively. The second switching circuit is configured to selectively couple the first PCM device and the second PCM device to output the first output signal or the second output signal.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 30, 2024
    Inventors: CHU-FENG LIAO, HUNG-PING CHENG, YUAN-YAO CHANG, SHUO-WEN CHANG
  • Publication number: 20240170336
    Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu