Abstract: Provided is the use of Bacteroides fragilis in the improvement and/or treatment of diarrhea. Tests of different mouse diarrhea models prove that Bacteroides fragilis ZY-312 with the deposit number CGMCC No. 10685 or inactivated Bacteroides fragilis ZY-312 has the effect of improving and treating diarrhea. The powder of the inactivated Bacteroides fragilis has a good effect of improving infectious diarrhea or non-infectious diarrhea in different concentrations of the formula, and has no side effects on the body.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: A semiconductor device includes a first fin-shaped structure and a second fin-shaped structure on a substrate, a bump between the first fin-shaped structure and the second fin-shaped structure, a first recess between the first fin-shaped structure and the bump, and a second recess between the second fin-shaped structure and the bump. Preferably, a top surface of the bump includes a curve concave upward, a width of the bump is greater than twice the width of the first fin-shaped structure, and a height of the bump is less than one fourth of the height of the first fin-shaped structure.

Abstract: Disclosed is a heart rate monitoring system containing a machine learning platform containing self-learning and/or personalizable algorithms capable of detecting and filtering out artifacts in signals indicative of an individual's heart rate, such signals generated from one or more electrocardiogram sensors. The self-learning and/or personalizable algorithms are updated periodically. Accordingly, the machine learning platform improves its accuracy in detecting and/or rejecting/filtering out artifacts and/or becomes more personalized as further signals indicative of an individual's heart rate are processed. The machine learning platform performs detection and filtering out of artifacts via dimension reduction algorithms. The system further contains a first algorithm for real time measurement of heart rate variability (HRV). Also disclosed is a heart rate monitoring method that implements a heart rate monitoring system disclosed herein.

Abstract: The present invention generally relates to a hydroponic culture medium and a hydroponic planting system, more particularly to a Houttuynia cordata hydroponic culture medium, a Houttuynia cordata hydroponic planting system, Houttuynia cordata extracts, a method, and applications thereof. The Houttuynia cordata hydroponic culture medium includes a plant fertilizer and a Houttuynia cordata growth-promoting additive. The Houttuynia cordata growth-promoting additive is selected from the group consisting of: vitamin B complex, seaweed essence, amino acid, microorganism, and a combination thereof. An electronic conductivity of the Houttuynia cordata hydroponic culture medium is between 0.4 ms/cm and 2.0 ms/cm.

Abstract: The disclosure relates to a light-emitting diode, which includes a semiconductor stacked structure, a channel, a first electrode, and a second electrode. The channel surrounds the semiconductor stacked structure. When viewed from above the light-emitting diode toward the semiconductor stacked structure, the semiconductor stacked structure has at least one chamfered portion located in the channel, and a range of a radius of curvature of the chamfered portion is from 5 to 50 microns. Through the optimization of the morphology of the LED chip epitaxial layer edges in the intersection region of the channel, the damage to the epitaxial layer caused by laser energy during stealth dicing is reduced, thereby achieving the objective of enhancing chip reliability.

Abstract: A server system includes a rack, servers disposed in the rack and a heat dissipation module including a pump assembly, a main manifold assembly, heat exchange assemblies and a sub manifold assembly. The pump assembly is disposed in the rack. The main manifold assembly includes two main pipelines, one is connected to a main outlet of the pump assembly and inlets of the servers, and the other is connected to outlets of the servers and a main inlet of the pump assembly. The heat exchange assemblies are removably disposed in the rack. The sub manifold assembly includes two sub pipelines, one is connected to a sub outlet of the pump assembly and inlets of the heat exchange assemblies, and the other is connected to outlets of the heat exchange assemblies and a sub inlet of the pump assembly.

Abstract: The present disclosure relates to aerosol delivery devices, methods of forming such devices, and elements of such devices. In some embodiments, the present disclosure provides a heating member that can be formed of a heating element conformed to a heater substrate configured as a truncated cone (or similar shape) having a first end of a first size and a second end of greater size. In some embodiments, the disclosure provides methods of forming an aerosol delivery device, which can include providing a shell, providing a heating member formed of a heating element conformed to a substrate, configuring the heating member as a truncated cone (or similar shape) having a first end of a first size and a second end of greater size, and inserting the heating member within the shell.

Abstract: A package structure and method of manufacturing a package structure are provided. The package structure includes two semiconductor structures and two bonding layers sandwiched between both semiconductor structures. Each bonding layer has a plurality of bonding pads separated by an isolation layer. Each bonding pad has a bonding surface including a bonding region and at least one buffer region. The bonding regions in both bonding layers bond to each other. The buffer region of one semiconductor structure bonds to the isolation layer of the other semiconductor structure. Each first bonding pad has a front cross-section with a length greater than a length of a front cross-section of each second bonding pads; and each second bonding pads has a side cross-section with a length greater than a length of a front cross-section of each first bonding pad.

Abstract: A moisture-permeable composite membrane is manufactured by the step of subjecting a mixture to a crosslinking treatment. The mixture contains a polyisoprene, a polyurethane with a polar functional group, a crosslinking agent, and a vulcanizing agent. In the mixture, a weight ratio of the polyurethane with the polar functional group to the polyisoprene ranges from 1:0.55 to 1:6.60. A method for manufacturing the moisture-permeable composite membrane is also provided.

Abstract: A semiconductor device includes a first semiconductor die that operates at a first power, a second semiconductor die that is formed in a stack on the first semiconductor die and operates at a second power different than the first power, and a power management semiconductor die that is formed in the stack and provides the first power to the first semiconductor die through a first via and provides the second power to the second semiconductor die through a second via.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: A semiconductor package includes a first connection die including a semiconductor substrate and an interconnect structure, and a first die stack disposed on the first connection die and including stacked dies, each of the stacked dies including a semiconductor substrate and an interconnect structure including a first connection line that is electrically connected to the interconnect structure of the first connection die. An angle formed between a plane of the first connection die and a plane of each stacked die ranges from about 45° to about 90°.

Abstract: An optical detection system integrating tonometer and autorefractor includes first and second optical modules. The first optical module includes a light source, first and second lens sets, a reflector, a first light-splitter and a sensor. The first lens set and reflector are disposed corresponding to light source. The first light-splitter is disposed corresponding to the reflector, second lens set and sensor. The second optical module includes a second light-splitter and first to third optical elements. The incident light emitted by the light source passes through the first lens, reflected by the reflector, passes through the first light-splitter, reflected by the second light-splitter, passes through the first to third optical elements and emitted to an eye. A sensing light from the eye passes through the third to first optical elements, reflected by the second light-splitter and first light-splitter, passes through the second lens set and emitted to the sensor.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.

Abstract: An array of complementary die sets is attached to a carrier substrate. A continuous complementary-level molding compound layer is formed around the array of complementary die sets. An array of primary semiconductor dies is attached to the array of complementary die sets. A continuous primary-level molding compound layer is formed around the array of primary semiconductor dies. The bonded assembly is diced by cutting along directions that are parallel to edges of the primary semiconductor dies. The sidewalls of the complementary dies are azimuthally tilted relative to sidewalls of the primary semiconductor dies, or major crystallographic directions of a single crystalline material in the carrier substrate are azimuthally tilted relative to sidewalls of the primary semiconductor dies.

Abstract: A circuit board assembly in a camera module for blocking unwanted light when images are captured includes a circuit board, a sensor, and an optical blocking body connecting the circuit board and the sensor. The circuit board includes a base board and a photomask. The photomask is arranged on a surface of the base board, the base board includes conductive circuit layers and dielectric layers, the conductive circuit layers and the dielectric layers are alternately arranged, the sensor being electronically connected to the conductive layers. The optical blocking body, the photomask, and the dielectric layers block ambient light entering the camera module other than through the lens assembly of the camera module.

Abstract: The present invention provides a cationic ?-cyclodextrin and a preparation method and uses thereof, as well as a cationic ?-cyclodextrin functionalized silver nanoparticles and a preparation method and uses thereof. The cationic ?-cyclodextrin of the present invention is introduced with an amine group and quaternary ammonium groups, while retaining the special structure and properties of cyclodextrin itself. The amine group contained in the structure plays a role in reducing and complexing Ag+ in the synthesis of AgNPs, and plays a certain role in stabilizing nanoparticles and forming a complex in combination with quaternary ammonium groups.

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a magnetic tunneling junction (MTJ) on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes metal and the blocking layer includes a grid line pattern according to a top view.