Patents by Inventor An-Ping Lee

An-Ping Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250127999
    Abstract: A droplet delivery device includes a droplets outlet coupled to a one-piece and removable container assembly, wherein the container assembly includes a mesh and a membrane, and wherein the mesh includes a plurality of openings formed through the mesh's thickness, a reservoir in fluid communication with the container assembly and configured to supply a volume of fluid, and a vibrating member coupled to a power source and positioned to cooperate with the membrane and mesh to generate an ejected stream of droplets through the mesh.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 24, 2025
    Applicant: PNEUMA RESPIRATORY, INC.
    Inventors: Charles Eric Hunter, Michael Scoggin, Jeffrey Miller, Jose Salazar, Brian Beach, Caley Modlin, Matthew Culpepper, Jianqiang Li, Chengjie Li, Shi Bo Wang, Chao-Ping Lee, Gregory Rapp, Judson Sidney Clements
  • Patent number: 12267420
    Abstract: Encrypted export controlled items within a corporate asset infrastructure may be searched for vendor access. Different versions of an export policy may change the ways in which the search is performed based on calculation of a numerical representation of a classification to identify the best forwarding location for a vendor access that is not subject to a Restricted Destination List. An indexing value may be determined, transparently with respect to a vendor, based on a desired plaintext item of data and a redacted technical data list. The indexing value may be used to access an entry in an indexing structure to obtain a corresponding document-oriented record which includes an encrypted ciphertext item. Positions of items of the indexing structure may be based on corresponding plaintext items.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: April 1, 2025
    Inventor: Yuen Ping Lee
  • Patent number: 12261149
    Abstract: A manufacturing method of a semiconductor structure including the following steps is provided. A first substrate is provided. A first dielectric structure is formed on the first substrate. At least one first cavity is formed in the first dielectric structure. A first stress adjustment layer is formed in the first cavity. The first stress adjustment layer covers the first dielectric structure. A second substrate is provided. A second dielectric structure is formed on the second substrate. At least one second cavity is formed in the second dielectric structure. A second stress adjustment layer is formed in the second cavity. The second stress adjustment layer covers the second dielectric structure. The first stress adjustment layer and the second stress adjustment layer are bonded.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 25, 2025
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Shih-Hsorng Shen, Chih-Wei Su, Yu-Chun Huo
  • Patent number: 12248835
    Abstract: The present disclosure provides a method for anti-tampering apparatus servicing data implemented by a calculation device connected to a target device, the method comprising: identifying a contract identification code and obtaining a contract package file and a contract authentication code from at least one remote device; obtaining a microservice file corresponding to the target device from the remote device when a device embedded code of the calculation device is matching the contract authentication code; performing the microservice file to enable the target device according to the contract package file and generate an execution report; publishing the execution report to the remote device to obtain an acceptance certification code; and combining and hashing the device embedded code, the contract authentication code and the acceptance certification code to generate a hash value, and sending the hash value to a blockchain.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: March 11, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Min-Hao Li, Yu-Chiao Wang, Ya-Ping Lee, Wei-Der Chung, Jhy-Ping Wu
  • Publication number: 20250075933
    Abstract: A building chiller/heat pump system includes a chiller/heat pump system for supplying a conditioned fluid to change a temperature of air being delivered into a building. The chiller/heat pump system is provided with a control to achieve a desired setpoint of the air delivered into the building. The control is programmed to receive a prediction of expected remission levels in energy that will be delivered to power the chiller/heat pump system. The control is programmed to change the setpoint such that an energy level required to operate the chiller/heat pump system to achieve the setpoint will drop when the expected emissions level increases, and adjusts the setpoint in an opposed direction when the expected emissions drops. A method is also disclosed.
    Type: Application
    Filed: August 28, 2024
    Publication date: March 6, 2025
    Inventors: Wei Huang, Lei Yu, Claus Daniel, Stella Maris Oggianu, Runfu Shi, Guy DeLuca, Mark Makwinski, Rebecca Shen, Mann-Fai Yip, Shaw Ping Lee, Chai Kheh Chew
  • Publication number: 20250029949
    Abstract: A wafer stacking process is provided in the present invention, including steps of forming a silicon oxide layer on a sacrificial carrier, bonding the silicon oxide layer with a dielectric layer on a front side of a silicon substrate, performing a thinning process on the back side of the silicon substrate to expose TSVs therewithin, bonding the back side of the silicon substrate with another silicon substrate, repeating the thinning process and the process of bonding another silicon substrate above so as to form a wafer stacking structure, and performing a removing process to completely remove the sacrificial carrier.
    Type: Application
    Filed: November 1, 2023
    Publication date: January 23, 2025
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chih-Feng Sung, Chih-Hao Chuang, Chun-Lin Lu, Shih-Ping Lee, Li-Han Chiu, Yi-Kai Wu
  • Patent number: 12203960
    Abstract: A manufacturing process for electrode of neuromodulation probe includes the steps of: preparing a plurality of the manufacturing fixtures for electrode of neuromodulation probe; preparing a plurality of the manufacturing fixtures for electrode in a surrounding manner by having the first-layer frames to be externally disposed side by side with the bevels of the two neighboring first-layer frames close to each other, so that the second-layer frames, the plurality of electrodes and the plurality of wires are enclosed thereinside; placing a cylinder amid the plurality of manufacturing fixtures for electrode to have the plurality of wires to surround the cylinder; having a fluid plastic to surround the cylinder by filling all the spaces between the plurality of wires and the plurality of electrodes, and waiting the fluid plastic to cure; removing the plurality of first-layer frames and the plurality of second-layer frames; and, pulling off the cylinder.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: January 21, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jo-Ping Lee, Kun-Ta Wu, Wei-Chin Huang, An-Li Chen
  • Patent number: 12199179
    Abstract: A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region in the first well region, the deep drain doped region has the first conductivity type.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: January 14, 2025
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Hirokazu Fujimaki, Bo-An Tsai, Shih-Ping Lee
  • Publication number: 20250006757
    Abstract: An image sensor includes a substrate, a global shutter component, a ground doped region, and a light-shielding layer. The substrate at least has a pixel array region and a border region adjacent to each other. The global shutter component is located on the pixel array region, and the global shutter component includes a storage node. The ground doped region is located on the border region. The light-shielding layer is located on the pixel array region and the border region and is electrically connected to the ground doped region. The light-shielding layer includes a first light-shielding layer and a second light-shielding layer. The first light-shielding layer is located on the pixel array region and covers the storage node, and the second light-shielding layer is located on the border region and surrounds the global shutter component. A manufacturing method of an image sensor is also provided.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 2, 2025
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Peng-Tse Chen, Chih-Ping Chung
  • Publication number: 20240379820
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
  • Publication number: 20240355628
    Abstract: A wafer processing method including following steps is provided. A release layer is formed on a first wafer. An adhesive layer is formed on a second wafer. One of the first wafer and the second wafer is a device wafer. The device wafer includes a valid die region and a trimming region. A handler is applied to place the first wafer on the second wafer, so that the release layer and the adhesive layer are bonded to each other, and the adhesive layer completely covers the valid die region. During the process of placing the first wafer on the second wafer, the handler directly moves the first wafer.
    Type: Application
    Filed: May 23, 2023
    Publication date: October 24, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chun-Fu Wu, Shih-Ping Lee, Yu-Chun Huo, Chih Feng Sung, Ming-Jui Tsai
  • Publication number: 20240355684
    Abstract: A wafer stacking method includes the following steps. A first wafer is provided. A second wafer is bonded to the first wafer to form a first wafer stack structure. A first edge defect inspection is performed on the first wafer stack structure to find a first edge defect and measure a first distance in a radial direction between an edge of the first wafer stack structure and an end of the first edge defect away from the edge of the first wafer stack structure. A first trimming process with a range of a first width is performed from the edge of the first wafer stack structure to remove the first edge defect. Herein, the first width is greater than or equal to the first distance.
    Type: Application
    Filed: May 4, 2023
    Publication date: October 24, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chih Feng Sung, Wei Han Huang, Ming-Jui Tsai, Yu Chi Chen, Yung-Hsiang Chang, Chun-Lin Lu, Shih-Ping Lee
  • Patent number: 12107149
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
  • Publication number: 20240312788
    Abstract: A method includes forming a fin protruding from a substrate, the fin including an epitaxial stack over a fin base and a hard mask layer over the epitaxial stack, the epitaxial stack including first and second semiconductor layers of different material compositions, performing a first etching process to etch the hard mask layer, the first etching process including applying a first combination of etchants, performing a second etching process to etch the epitaxial stack, the second etching process including applying a second combination of etchants, and performing a third etching process to etch the fin base, the third etching process including applying a third combination of etchants. The first, second, and third combinations of etchants are different from each other.
    Type: Application
    Filed: August 18, 2023
    Publication date: September 19, 2024
    Inventors: Shin-Li WANG, Szu-Ping LEE, Zu-Yin LIU, You-Ting LIN, Jiun-Ming KUO, Chun-Hung LEE, Yuan-Ching PENG
  • Publication number: 20240304628
    Abstract: In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.
    Type: Application
    Filed: May 7, 2024
    Publication date: September 12, 2024
    Inventors: Wan-Yi Kao, Szu-Ping Lee, Che-Hao Chang, Chun-Heng Chen, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20240282579
    Abstract: The invention provides a manufacturing method of a semiconductor structure, which includes the following. A substrate is provided. The substrate includes a region of a first conductivity type. A patterned photoresist layer is formed on the substrate. The patterned photoresist layer includes a main portion and a split portion separated from each other. An ion implantation process is performed on the substrate by using the patterned photoresist layer as a mask to form a well region in the region of the first conductivity type. The well region has a second conductivity type. The main portion and the split portion are adjacent to the same end terminal of the well region.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 22, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Mao-Teng Hsu, Shih-Ping Lee, Kuo-Tung Peng
  • Publication number: 20240269397
    Abstract: A droplet delivery device includes a housing with a mouthpiece port or outlet from a nasal device for releasing fluid droplets, a fluid reservoir, and an ejector bracket having a membrane positioned between a mesh with a plurality of openings and a vibrating member that is coupled to an electronic transducer, such as an ultrasonic transducer. The transducer vibrates the vibrating member which causes the membrane to push fluid supplied by the reservoir through the mesh to generate droplets in an ejected stream released through the outlet.
    Type: Application
    Filed: October 23, 2023
    Publication date: August 15, 2024
    Applicant: PNEUMA RESPIRATORY, INC.
    Inventors: Charles Eric Hunter, Michael Scoggin, Jeffrey Miller, Jose Salazar, Brian Beach, Caley Modlin, Matthew Culpepper, Jianqiang Li, Chengjie Li, Shi Bo Wang, Chao-Ping Lee, Gregory Rapp, Judson Sidney Clements
  • Publication number: 20240242304
    Abstract: A ride sharing implementation includes a system for logically grouping users. The logical groups may include one or more users designated as riders and one or more users designated as drivers. Notifications for ride requests submitted by or on behalf of riders are transmitted to drivers who can then accept the requests to coordinate transportation of the riders. Example personal monitoring devices and mobile applications for facilitating ride sharing are also provided.
    Type: Application
    Filed: May 6, 2022
    Publication date: July 18, 2024
    Inventors: Jack C. HUNTER, Chao-Ping LEE, FuQing FAN
  • Patent number: 12037670
    Abstract: A nano-twinned Cu—Ni alloy layer is provided, wherein more than 50% in volume of the nano-twinned Cu—Ni alloy layer comprises plural twinned grains, the plural twinned grains comprise plural columnar twinned grains, and a Ni content in the nano-twinned Cu—Ni alloy layer is in a range from 0.05 at % to 20 at %. In addition, a method for manufacturing the aforesaid nano-twinned Cu—Ni alloy layer is also provided.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: July 16, 2024
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chih Chen, Kang-Ping Lee, Yu-I Chang, Yun-Hsuan Chen
  • Publication number: 20240228525
    Abstract: The present invention discloses a glucosamine derivative nanoparticle and preparation method and use thereof. By self-assembling glucosamine derivatives and ethanol into the form of nanoparticles, the skin penetration rate and cell absorption rate of glucosamine are improved, and at the same time the toxicity to cells and organisms is reduced. The problem of poor absorption of glucosamine is improved by using glucosamine derivative nanoparticles. Furthermore, the glucosamine derivative nanoparticles can be used as a delivery carrier to cover and bring the specified ingredients into the cells or stratum corneum, and to increase the skin penetration rate and cell absorption rate of the specified ingredients.
    Type: Application
    Filed: March 6, 2023
    Publication date: July 11, 2024
    Inventors: Hsiao-Ping Lee, Chien-Chung Cheng, Jeen-Kuan Chen, Hsin-Yi Lee