Abstract: A method of forming an image sensor includes forming a photodiode within a semiconductor substrate. The method further includes disposing an interconnect structure over the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL) over the photodiode; and a plurality of dielectric layers over the CESL, wherein at least one dielectric layer of the plurality of dielectric layers comprises a low dielectric constant (low-k) material. The method further includes patterning at least the plurality of dielectric layers, wherein patterning at least the plurality of dielectric layers comprises defining an opening above an active region of the photodiode. The method further includes depositing a cap layer on sidewalls of the opening, wherein the cap layer includes a dielectric material having a higher moisture resistance than the low-k dielectric material.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: A method and a system for identifying an operating status of an electrical appliance based on non-intrusive load monitoring are provided. The method includes the following steps. Total power consumption history data of a target field and appliance power consumption history data of target electrical appliances are obtained. The appliance power consumption history data of each target electrical appliance is converted into a binary data set. The total power consumption history data is clustered into cluster samples to obtain first feature data sets, which are then dimensionally reduced into second feature data sets, and a machine learning model is trained by using the second feature data sets and the binary data sets of the target electrical appliances to establish an operation identification model for the target electrical appliances. The operation identification model identifies an operating status of the target electrical appliances according to total power consumption data.

Abstract: A cleaning process monitoring system, comprising: a cleaning container comprising an inlet for receiving a cleaning solution and an outlet for draining a waste solution; a particle detector coupled to the outlet and configured to measure a plurality of particle parameters associated with the waste solution so as to provide a real-time monitoring of the cleaning process; a pump coupled to the cleaning container and configured to provide suction force to draw solution through the cleaning system; a controller coupled to the pump and the particle detector and configured to receive the plurality of particle parameters from the particle detector and to provide control to the cleaning system; and a host computer coupled to the controller and configured to provide at least one control parameter to the controller.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Abstract: An optical device is provided. The optical device has a central region and a first-type region surrounding the central region. The first-type region includes a first sub-region and a second sub-region between the central region and the first sub-region. The optical device includes a substrate. The optical device also includes a meta-structure disposed on the substrate. The meta-structure includes first pillars in the first sub-region and second pillars in the second sub-region. In the cross-sectional view of the optical device along the radial direction of the optical device, two adjacent first pillars have a first pitch, two adjacent second pillars have a second pitch, and the second pitch is greater than the first pitch.

Abstract: An electronic device is provided. The electronic device includes a first substrate, a multilayer structure, and a passivation layer. The multilayer structure is disposed on the first substrate. The multilayer structure includes a first conductive layer and a second conductive layer disposed on the first conductive layer. The passivation layer is disposed on the second conductive layer. In addition, a thermal expansion coefficient of the second conductive layer is between a thermal expansion coefficient of the first conductive layer and a thermal expansion coefficient of the passivation layer.

Abstract: A method includes depositing a first dielectric layer on a first substrate of a first device die, etching the first dielectric layer to form a trench, depositing a metallic material in the trench and on a top surface of the first dielectric layer, and performing a chemical mechanical polish (CMP) process to remove a portion of the metallic material from the top surface of the first dielectric layer to form a first metal pad. After the performing of the CMP process, the method selectively etches the first metal pad to form recesses at an edge portion of the first metal pad, deposits a second dielectric layer on a second substrate of a second device die, forms a second metal pad in the second dielectric layer, and bonds the second device die to the first device die.

Abstract: A modulation device includes a substrate, a metal layer, at least one driving element, and a modulation unit. The metal layer is disposed on the substrate and has at least one hole. The at least one driving element is disposed on the substrate and overlapped with the at least one hole. The modulation unit is electrically connected to the at least one driving element.

Abstract: The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a flexible substrate, an adhesive layer, a metal layer, a driving unit, and a modulating unit. The adhesive layer is disposed on the flexible substrate. The metal layer is disposed on the adhesive layer. The driving unit is disposed on the adhesive layer. The modulating unit is disposed on the adhesive layer. The manufacturing method of the electronic device includes the following steps: providing a carrier substrate; forming a first metal layer on the carrier substrate; providing a flexible substrate, and combining the flexible substrate and the carrier substrate; removing the carrier substrate; and providing a modulating unit, and disposing the modulating unit on the flexible substrate. The electronic device and the manufacturing method thereof of the embodiments of the disclosure may make the electronic device having the modulating unit applicable to a non-planar structure.

Abstract: The disclosure provides an electronic apparatus. The electronic apparatus includes a substrate, a first metal layer, an insulating layer, a first conductor, an electronic assembly and a transistor circuit die. The first metal layer is disposed on the substrate. The insulating layer is disposed on the substrate. The first conductor is formed in a first via of the insulating layer. The electronic assembly is disposed on the substrate and electrically connected to the first metal layer through the first conductor. The transistor circuit die is electrically connected to the first metal layer.

Abstract: A sensor is provided, including a substrate, a chip and a sensing element. The substrate has a plate-like shape and includes a surface and an interconnect structure disposed in the substrate. The chip is embedded in the substrate and is electrically connected to the interconnect structure. The sensing element is disposed on the surface of the substrate, and is electrically connected to the chip through the interconnect structure.

Abstract: A manufacturing method of an electronic device is provided, which includes following steps. A substrate is provided. A conductive layer is formed on the substrate. A circuit structure is formed on the conductive layer. The circuit structure is patterned to form at least one opening. The at least one opening has a stepped profile. An electronic device is also provided.

Abstract: An electronic device including a substrate, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a bonding structure, and a chip is provided. The first conductive layer is disposed on the substrate. The first insulating layer is disposed on the first conductive layer and has a first via. The second conductive layer is disposed on the first insulating layer, wherein the second conductive layer is electrically connected to the first conductive layer through the first via. The second insulating layer is disposed on the second conductive layer and has a second via. The bonding structure is disposed on the second insulating layer, wherein the bonding structure is electrically connected to the second conductive layer through the second via. The chip is disposed on the bonding structure.

Abstract: An electronic device including a substrate, a conductive layer, a first driving component, and an electronic component is provided. The conductive layer is disposed on the substrate. A thickness of the conductive layer is between 0.5 ?m and 12 ?m. The first driving component is disposed on the conductive layer. The electronic component is disposed on the substrate and electrically connected to the first driving component.

Abstract: The disclosure provides an electronic device including a substrate, at least one conductive composite structure, and an electronic element. The at least one conductive composite structure is disposed on the substrate. The at least one conductive composite structure includes a first metal layer, a second metal layer, and a third metal layer. The second metal layer is located between the first metal layer and the third metal layer, and the thickness of the second metal layer ranges from 0.5 ?m to 12 ?m. The electronic element is disposed on the at least one conductive composite structure and bonded to the at least one conductive composite structure.

Abstract: An electronic device including a substrate, a first metal pattern, a first insulating pattern, and a second metal pattern is provided. The first metal pattern is disposed on the substrate. The first insulating pattern is disposed on the first metal pattern. The second metal pattern is disposed on the first metal pattern and the first insulating pattern. The second metal pattern includes a first contact portion and a second contact portion. In a cross-sectional view, the first contact portion and the second contact portion are in contact with the first metal pattern, and the first insulating pattern is in contact with the first metal pattern and the second metal pattern between the first contact portion and the second contact portion.