Patents by Inventor An Shih

An Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250120301
    Abstract: Provided are organometallic compounds comprising a ligand comprising at least two moieties A and B which are linked by a linking group L2, wherein the ligand is coordinated to a central metal atom M. Also provided are formulations comprising these organometallic compounds. Further provided are organic light emitting devices (OLEDs) and related consumer products that utilize these organometallic compounds.
    Type: Application
    Filed: September 16, 2024
    Publication date: April 10, 2025
    Applicant: UNIVERSAL DISPLAY CORPORATION
    Inventors: Hsiao-Fan Chen, Wystan Neil Palmer, Jui-Yi Tsai, Wei-Chun Shih, Zhiqiang Ji
  • Publication number: 20250120167
    Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface, and an etch stop layer extends between the portion of the bottom surface of the gate spacer and the top surface of the topmost semiconductor layer.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
  • Publication number: 20250120097
    Abstract: A memory device includes a two-dimensional array of access transistors located on a semiconductor substrate; metal interconnect structures embedded in dielectric material layers and electrical connected to electrical nodes of the access transistors; and a two-dimensional array of resistive memory structures embedded in the dielectric material layers. The metal interconnect structures include two first source lines located at a first metal line level and laterally extending along a first horizontal direction; a second source line located at a second metal line level and laterally extending along the first horizontal direction; and a vertical connection structure including a plurality of interconnection via structures and at least one line-level metal structure and providing a vertical electrical connection between the two first source lines and the second source line.
    Type: Application
    Filed: April 8, 2024
    Publication date: April 10, 2025
    Inventors: Sheng-Hung Shih, Kuo-Chi Tu, Wan-Chen Chen, Tzu-Yu Chen, Wen-Ting Chu
  • Publication number: 20250120151
    Abstract: A method of fabricating a semiconductor structure includes forming a recess in an active channel structure by removing a portion thereof, filling the recess with a dielectric material, forming a cladding layer adjacent the active channel structure but not adjacent the dielectric material, and forming a gate structure comprising a first gate structure and a second gate structure around the active channel structure. A width of the dielectric material in the recess is greater than a width of the first gate structure and a width of the second gate structure.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: KUEI-YU KAO, Shih-Yao LIN, Chen-Ping Chen, Chih-Han Lin, MING-CHING CHANG, CHAO-CHENG CHEN
  • Publication number: 20250120161
    Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Tsai, Jung Han, Ming-Chi Li, Chih-Mou Lin, Yu-Hsiang Hung, Yu-Hsiang Lin, Tzu-Lang Shih
  • Publication number: 20250114908
    Abstract: A system may include a gimbal defining a plurality of pockets, where each pocket may include a first portion and a second portion that extends between the first portion and a base of the pocket. The second portion may have a greater diameter than the first portion. The system may include a plurality of conditioning disks, where each conditioning disk is seated within the first portion of a respective pocket. The system may include a plurality of gaskets, where each gasket is seated within the second portion of a respective pocket. The system may include a plurality o-rings, each o-ring disposed between a peripheral edge of one of the plurality of conditioning disks and a lateral wall of one of the plurality of pockets. The system may include a plurality of shoulder screws for coupling the gimbal with one of the plurality of gaskets and a conditioning disk.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 10, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Nai-Chieh Huang, Akshay Aravindan, Shih-Haur Shen, Jianshe Tang, Jay Gurusamy, Chen-Wei Chang, Chih-Han Yang, Wei Lu
  • Publication number: 20250119813
    Abstract: A transmission channel switching method is provided. The transmission channel switching method may include the following steps. An apparatus may establish a plurality of transmission channels. The apparatus may transmit data through a default transmission channel of the transmission channels, wherein the default transmission channel corresponds to the lowest power consumption. The apparatus may determine whether to switch to another transmission channel of the transmission channels according to channel quality of each transmission channel and power consumption corresponds to each transmission channel.
    Type: Application
    Filed: September 23, 2024
    Publication date: April 10, 2025
    Inventors: Wei-Shuo CHEN, Kun-Lin WU, Pang-Hsin SHIH, Yuan-Chin WEN, Te-Hsin LIN, Cheng-Che CHEN
  • Publication number: 20250120123
    Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent the gate dielectric layer, wherein the first gate spacer comprises an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface towards the outer surface of the first gate spacer.
    Type: Application
    Filed: January 24, 2024
    Publication date: April 10, 2025
    Inventors: Chun-Fu LU, Lung-Kun CHU, Jia-Ni YU, Chung-Wei HSU, Shih-Hao LAI, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250115922
    Abstract: The present invention provides for a nucleic acid encoding refactored minimized set of Agrobacterium virulence genes. The present invention provides for a method for introducing a nucleic acid of interest into a eukaryotic cell, the method comprises: (a) providing (i) a first nucleic acid encoding a refactored minimized set of Agrobacterium virulence genes operatively linked to one or more promoters; and (ii) a second nucleic acid comprising a nucleic acid of interest flanked by a left border and a right border; (b) introducing the first nucleic acid and the second nucleic acid into a target host cell; and, (c) the nucleic acid of interest is stably integrated into a genome of the target host cell.
    Type: Application
    Filed: October 4, 2024
    Publication date: April 10, 2025
    Inventors: Mitchell G. THOMPSON, Allison N. PEARSON, Patrick M. SHIH
  • Publication number: 20250120122
    Abstract: One aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a semiconductor substrate and a transistor formed over the semiconductor substrate. The transistor includes a first source/drain (S/D) feature, a second S/D feature, a channel region interposed between the first and second S/D features, and a gate stack engaging the channel region. The semiconductor device includes a first S/D contact landing on a top surface of the first S/D feature, a second S/D contact landing on a top surface of the second S/D feature, and a dielectric plug penetrating through the semiconductor substrate and landing on a bottom surface of the first S/D feature. The dielectric plug spans a width equal to or smaller than a width of the first S/D feature.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 10, 2025
    Inventors: Chen-Ming Lee, Shih-Chieh Wu, Po-Yu Huang, I-Wen Wu, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20250118619
    Abstract: A method includes forming a bonding structure that contains thermal conductive vias (also termed as thermal vias, thermal conductive pillars, or thermal pillars) on a semiconductor structure. The thermal vias, with material thermal conductivity greater than about 10 W/m·K, are embedded in the bonding structure that provides a quick dissipation path of heat from thermal hotspot regions into a substrate.
    Type: Application
    Filed: March 12, 2024
    Publication date: April 10, 2025
    Inventors: Yung-Ta Chen, Kuan-Kan Hu, Chun-Yu Liu, Che Chi Shih, Ku-Feng Yang, Szuya Liao
  • Publication number: 20250119367
    Abstract: Systems, methods, and computer-readable media are provided for generating a unique ID for a sensor in a network. Once the sensor is installed on a component of the network, the sensor can send attributes of the sensor to a control server of the network. The attributes of the sensor can include at least one unique identifier of the sensor or the host component of the sensor. The control server can determine a hash value using a one-way hash function and a secret key, send the hash value to the sensor, and designate the hash value as a sensor ID of the sensor. In response to receiving the sensor ID, the sensor can incorporate the sensor ID in subsequent communication messages. Other components of the network can verify the validity of the sensor using a hash of the at least one unique identifier of the sensor and the secret key.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Inventors: Abhishek Ranjan Singh, Shih-Chun Chang, Varun Sagar Malhotra, Hai Trong Vu, Jackson Ngoc Ki Pang
  • Publication number: 20250117079
    Abstract: In some embodiments, an electronic device facilitates cursor interactions in different regions in a three-dimensional environment. In some embodiments, an electronic device facilitates cursor interactions in content. In some embodiments, an electronic device facilitates cursor movement. In some embodiments, an electronic device facilitates interaction with multiple input devices. In some embodiments, a computer system facilitates cursor movement based on movement of a hand of a user of the computer system and a location of a gaze of the user in the three-dimensional environment. In some embodiments, a computer system facilitates cursor selection and scrolling of content in the three-dimensional environment.
    Type: Application
    Filed: October 15, 2024
    Publication date: April 10, 2025
    Inventors: Shih-Sang CHIU, Christopher D. MCKENZIE, Pol PLA I CONESA, Jonathan RAVASZ, Benjamin H. BOESEL, Evgenii KRIVORUCHKO, Zoey C. TAYLOR
  • Publication number: 20250114905
    Abstract: A system and method for chemical mechanical polishing (“CMP”) pad replacement on a CMP processing tool. A platen carrier having two or more platens is positioned within a platen cleaning process module. Each platen includes a CMP pad affixed thereto, and is capable of being independently rotated during operations. When a pad requires replacement, the platen carrier rotates towards a pad tearer tool, which extends and pivots to remove the used pad from the platen as the carrier rotates. A pad tape replacement module is positioned above the CMP tool with pad tape extending from a supply roll to a recycle roll. As the pad tape transits through the module, a backing of the tape is separated and recycled. A pad disposed in the pad tape is then applied to a platen via a pressure roller.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Inventors: Shih-Chung Chen, Wei-Kang Tu, Ching-Wen Cheng, Chun Yan Chen
  • Publication number: 20250116139
    Abstract: A casing latch structure is disclosed and includes a casing, a main body, a clamping element, a fastening element, and an abutting element. The casing includes a first wall and a second wall perpendicular to each other, a through hole disposed on the first wall, and a sliding groove disposed on the second wall. The main body includes a clamping portion, a sliding portion and a fastened portion. The sliding portion is connected between the clamping portion and the fastened portion arranged on two opposite sides of the second wall, and received in the sliding groove. The clamping element is sleeved between the sliding portion and the fastened portion. The fastening element is engaged with the fastened portion to lock or release the clamping portion. The abutting element includes an abutting portion and an embedded portion connected to each other and corresponding to the through hole and the sliding groove.
    Type: Application
    Filed: March 21, 2024
    Publication date: April 10, 2025
    Inventors: Yi-Syuan Li, Shih-Ming Yan, Ching-Chuan Hsu
  • Publication number: 20250115708
    Abstract: An apparatus for producing solid crystallized polymer particles. The apparatus includes a precrystallizer followed by a static vessel. The crystallinity of the polyester is increased in the static vessel compared to the crystallinity of the polyester from the precrystallizer or the single crystallizer. Inert gas is fed to the static vessel to remove oligomers and fines from the chip and assist with chip mobility. It can optionally include a single crystallizer. The static vessel can replace one or both of the crystallizers in a conventional polyester process. A method for making polyester particles is also described.
    Type: Application
    Filed: July 3, 2024
    Publication date: April 10, 2025
    Inventors: Raymond Shih, Gianfranco Ballarin, Mulugeta Kebede
  • Publication number: 20250116761
    Abstract: An optical depth sensing apparatus includes a first light source emitting a first light beam having a first polarization state, a second light source emitting a second light beam having a second polarization state, a first sensing device sensing the first light beam and including a first metalens, and a second sensing device sensing the second light beam and including a second metalens. An electric field direction of the first polarization state is perpendicular to an electric field direction of the second polarization state. The first light beam having the first polarization state is transmitted to the first metalens, and the second light beam having the second polarization state is reflected or absorbed by the first metalens. The second light beam having the second polarization state is transmitted to the second metalens, and the first light beam having the first polarization state is reflected or absorbed by the second metalens.
    Type: Application
    Filed: August 2, 2024
    Publication date: April 10, 2025
    Applicant: GUANGZHOU LUXVISIONS INNOVATION TECHNOLOGY LIMITED
    Inventors: Tzu-Yao Lin, Shih-Chieh Yen
  • Publication number: 20250117642
    Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Inventors: Win-San KHWA, Yu-Der CHIH, Yi-Chun SHIH, Chien-Yin LIU
  • Publication number: 20250117442
    Abstract: An online concierge system receives unstructured data describing items offered for purchase by various warehouses. To generate attributes for products from the unstructured data, the online concierge system extracts candidate values for attributes from the unstructured data through natural language processing. One or more users associate a subset candidate values with corresponding attributes, and the online concierge system clusters the remaining candidate values with the candidate values of the subset associated with attributes. One or more users provide input on the accuracy of the generated clusters. The candidate values are applied as labels to items by the online concierge system, which uses the labeled items as training data for an attribute extraction model to predict values for one or more attributes from unstructured data about an item.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 10, 2025
    Inventors: Shih-Ting Lin, Jonathan Newman, Min Xie, Haixun Wang
  • Publication number: 20250117035
    Abstract: A reference voltage generator includes an input terminal configured to receive an enable signal and an output terminal configured to provide an output signal. A voltage generator circuit is arranged to generate a first output voltage signal, and a pre-settling circuit is arranged to generate a second output voltage. The pre-settling circuit is configured to provide the second output voltage signal at the output terminal in response to the enable signal received at the input terminal, and following a first time period provide the first output voltage at the output terminal.
    Type: Application
    Filed: November 6, 2024
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-An Chang, Yi-Chun Shih, Chieh-Pu Lo