Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

Abstract: This disclosure is directed to a circuit that includes a substrate, a target device on the substrate, and an electrostatic discharge (ESD) device electrically coupled to the target device. The ESD device includes an ESD detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply, an inverter circuit electrically coupled to the ESD detection circuit and configured to trigger in response to an ESD event on the first or second reference voltage supply, a rectifier circuit electrically coupled to the inverter circuit and configured to rectify a current discharged from the inverter circuit, and a transistor electrically coupled to the rectifier circuit and configured to discharge a remaining current passing through the rectifier circuit.

Abstract: A display apparatus includes a driving backplane, a plurality of light emitting components, a first bank layer and a plurality of scattering particles. The first bank layer is disposed on the driving backplane. The first bank layer has a plurality of first openings and a plurality of oblique surfaces defining the first openings. The light emitting components respectively overlap with the first openings of the first bank layer. The scattering particles are disposed on a plurality of light emitting surfaces of the light emitting components. A plurality of air gaps exist between the scattering particles and the oblique surfaces of the first bank layer.

Abstract: A semiconductor device with an image sensor and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a pixel region with a pixel structure, an isolation region with an isolation structure disposed adjacent to the pixel region, and a contact pad region with a pad structure disposed adjacent to the isolation region. The pixel structure includes an epitaxial structure, which includes an embedded portion with a stepped structure disposed in the substrate and a protruding portion extending above a top surface of the substrate. The pixel structure further includes a capping layer disposed on the protruding portion.

Abstract: A method for forming a semiconductor device structure includes forming nanostructures over a substrate. The method also includes forming a gate structure wrapped around the nanostructures. The method also includes forming source/drain epitaxial structures over opposite sides of the nanostructures. The method also includes forming a first interlayer dielectric structure over the source/drain epitaxial structures. The method also includes removing the first interlayer dielectric structure. The method also includes forming a recess in the source/drain epitaxial structures. The method also includes forming a silicide structure in the recess. The method also includes forming a second interlayer dielectric structure over the silicide structure.

Abstract: A semiconductor structure includes a ferroelectric layer and a semiconductor layer. Thee ferroelectric layer has a first surface and a second surface opposite to the first surface. The semiconductor layer is formed on one of the first surface and the second surface.

Abstract: A semiconductor device and methods of manufacture are discussed herein. A device includes a first semiconductor package including a first semiconductor die encapsulated in an insulating material, a first thermal expansion resistant layer over the first semiconductor die, a bonding layer over the first thermal expansion resistant layer and the insulating material, and a second semiconductor die directly bonded to the bonding layer.

Abstract: A package includes: a vertically extending first electronic component with at least one exposed electrically conductive first terminal; a vertically extending second electronic component with at least one exposed electrically conductive second terminal; and a clip with an accommodation volume in which the first electronic component and the second electronic component are accommodated and are held together. The at least one first terminal and the at least one second terminal are electrically accessible at a bottom of the clip.

Abstract: A compound E1 capable of functioning as an emitter an organic light emitting device (OLED) at room temperature is provided. The compound is a metal coordination complex; the metal coordination complex comprises a first ligand, LA, that comprises a first group; and the metal coordination complex comprises a covalent bond between the metal and the first group; wherein the transition dipole moment (TDM) of the emissive state of the complex has a vector, wherein an angle formed between the TDM vector and the covalent bond between the metal and the first group is less than or equal to 40°, and wherein an excited state of the metal coordination complex has a LC character localized on the first group of greater than or equal to 45%. Formulations, OLEDs, and consumer products containing the compound are also provided.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising first opposing sidewalls defining a first trench and second opposing sidewalls defining a second trench laterally offset from the first trench. A stack of layers comprises a plurality of conductive layers and a plurality of dielectric layers alternatingly stacked with the conductive layers. The stack of layers comprises a first segment in the first trench and a second segment in the second trench. A first lateral distance between the first segment and the second segment aligned with a first surface of the substrate is greater than a second lateral distance between the first segment and the second segment below the first surface of the substrate.

Abstract: Disclosed herein is a method for treating and/or preventing a lymphangiogenesis-associated disease in a subject, including administering to the subject a therapeutically effective amount of a dihydrolipoic acid (DHLA)-coated gold nanocluster about 0.1 to 10 nm in diameter. Also disclosed is a method for promoting lymphangiogenesis in a subject, including administering to the subject an effective amount of said DHLA-coated gold nanocluster.

Abstract: A memory circuit includes: a memory configured to store a data unit and a corresponding first code; a decoding circuit configured to do as follows including, generate a second code based on a read address associated with the stored data unit, and generate a decoded write address based on the second code; a first error detecting circuit configured to do as follows including, determine an address fault by performing a first comparison between the read address and the decoded write address, and generate an error signal indicative of a result of the first comparison.

Abstract: A memory device includes a peripheral substrate and an array substrate. The peripheral substrate includes a page buffer and a high voltage processing circuits and has a peripheral substrate area. The array substrate includes an array. The array substrate and the peripheral substrate are stacked on each other, and a circuit distribution area of the high voltage processing circuit accounts for less than 10% of the peripheral substrate area.

Abstract: An optical imaging lens includes six lens elements. The object-side surface of the first lens element has a convex part in a vicinity of the periphery of the first lens element, the image-side surface of the second lens element has a concave part in a vicinity of the periphery of the first lens element, the object-side surface of the third lens element has a convex part in a vicinity of the optical axis, the image-side surface of the fourth lens element has a convex part in a vicinity of the periphery of the fourth lens element, the image-side surface of the fifth lens element has a concave part in a vicinity of the optical axis, and the sixth lens element has negative refractive power.

Abstract: A driving circuit is provided. The driving circuit includes a first switch, a second switch, a temperature sensing circuit, and a control circuit. The first terminal of the first switch is configured to receive an input voltage. The first terminal of the second switch is coupled to the second terminal of the first switch, and the second terminal of the second switch is coupled to a ground. The temperature sensing circuit is configured to sense a temperature indicating signal. The control circuit is configured to receive a PWM control signal and the temperature indicating signal and provide an adjusted PWM control signal according to the PWM control signal and the temperature indicating signal. An on-time of the adjusted PWM control signal is different from an on-time of the PWM control signal.

Abstract: A method includes bonding a device die onto a package component. The device die includes a semiconductor substrate, and a through-via extending into the semiconductor substrate. The method further includes depositing a dielectric liner lining sidewalls of the device die, depositing a dielectric layer on the dielectric liner, and planarizing the dielectric layer and the device die. Remaining portions of the dielectric liner and the dielectric layer form a gap-filling region, and a top end of the through-via is revealed. An implantation process is performed to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer. A redistribution line is formed over and electrically connecting to the through-via.

Abstract: A manufacturing method of an electronic device is disclosed by the present disclosure. The manufacturing method includes providing a plurality of semiconductor elements; performing a packaging process on the plurality of semiconductor elements to form a plurality of packaged semiconductor elements, wherein the packaging process includes disposing a plurality of filling material layers respectively on a sidewall of each of the plurality of semiconductor elements; providing a substrate, wherein the substrate includes a plurality of working areas, and each of the plurality of working areas includes at least one first recess; and disposing the plurality of packaged semiconductor elements in the at least one first recess of each of the plurality of working areas through fluid transfer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base and a fin over the base. The method includes forming a first gate stack wrapped around the fin. The method includes forming a first gate spacer over a first sidewall of the first gate stack. The method includes partially removing the fin, which is not covered by the first gate stack and the first gate spacer. The method includes removing a first upper portion of the first gate stack to expose a second upper portion of the first gate spacer. The method includes removing the second upper portion of the first gate spacer. The method includes removing a first lower portion of the first gate stack and the fin originally wrapped by the first gate stack. The method includes forming a dielectric channel-cut structure in the trench.

Abstract: In one aspect, a first playback device is configured to (i) receive a set of voice signals, (ii) process the set of voice signals using a first set of audio processing algorithms, (iii) identify, from the set of voice signals, at least two voice signals that are to be further processed, (iv) determine that the first playback device does not have a threshold amount of computational power available, (v) receive an indication of an available amount of computational power of a second playback device, (vi) send the at least two voice signals to the second playback device, (vii) cause the second playback device to process the at least two voice signals using a second set of audio processing algorithms, (viii) receive, from the second playback device, the processed at least two voice signals, and (ix) combine the processed at least two voice signals into a combined voice signal.

Abstract: An automated system that can be used for prosthetic heart valve manufacturing or suturing procedures. The system can include a first automated fixture that includes an articulating arm and a target device holder. The system can also include one or more additional automated fixtures, which can be configured as one or more suturing arms that include another articulating arm and a needle holder. The first automated fixture can be configured to rotate a target device held by the holder to allow the one or more additional automated fixtures to perform operations such as form sutures on the target device without intervention of a human operator. The system can include a display system configured to display status information of a suturing procedure.