Abstract: A ferroelectric tunnel junction (FTJ) includes bottom and top electrodes and a ferroelectric layer disposed between the bottom and top electrodes. A dielectric material is disposed in a space between a peripheral area of the ferroelectric layer and a sidewall of the top electrode. At least one conformal dielectric spacer is deposited. The FTJ is annealed to induce ferroelectric phase crystallization in the ferroelectric layer. The depositing at least one conformal dielectric spacer includes at least one of: (i) prior to the disposing of the dielectric material, depositing an inner conformal dielectric spacer on the peripheral area of the ferroelectric layer and on the sidewall of the top electrode, and/or (ii) after the disposing of the dielectric material, depositing an outer conformal dielectric spacer on dielectric material and on a sidewall of the peripheral area of the ferroelectric layer.

Abstract: A semiconductor memory structure includes a gate structure, a ferroelectric layer over the gate structure, a channel layer over the ferroelectric layer, an intervening structure between the ferroelectric layer and the channel layer, and a source structure and a drain structure separated from each other over the channel layer. A thickness of the intervening structure is less than a thickness of the channel layer and less than a thickness of the ferroelectric layer. The channel layer and the intervening structure include different materials.

Abstract: A semiconductor structure includes a substrate, a piezoelectric layer, and a stress structure. The substrate includes a first surface and a second surface, wherein a portion of the substrate proximal to the first surface defines a diaphragm. The piezoelectric layer is disposed over the first surface of the substrate and surrounds the diaphragm, wherein the piezoelectric layer includes a first portion and a second portion arranged along a periphery of the diaphragm from a top view. The stress structure includes a plurality of dielectric layers disposed over the piezoelectric layer and between the substrate and the piezoelectric layer, and a total thickness of a first portion of the stress structure overlapping the first portion of the piezoelectric layer is different from a total thickness of a second portion of the stress structure overlapping the second portion of the piezoelectric layer. A method for manufacturing a semiconductor structure is also provided.

Abstract: A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.

Abstract: The present disclosure relates generally to coated abrasive articles that include a tribological performance enhancing composition in a make coat, a size coat, a supersize coat, or combinations thereof, as well as methods of making coated abrasive articles. The present disclosure also relates to coated abrasive articles including a supersize coating comprising a sulfide scavenging composition and/or a crosslinked zinc acrylic binder, as well as methods for making and using such abrasive articles. The present disclosure also relates generally to abrasive articles that include aggregates having an anti-wear composition or grinding aid disposed on or within the aggregates.

Abstract: An electric assistive device is provided. The electric assistive device includes a power wheel module, an upper control module, and a power control module. The upper control module is configured to provide a dynamic characteristic parameter. The power control module is coupled to the power wheel module and the upper control module. In response to operating the electric assistive device in an auxiliary walking mode, the power control module adaptively generates a first vehicle speed parameter according to a dynamic characteristic parameter and a force estimation parameter. The power control module generates a voltage control signal according to the first vehicle speed parameter. The power control module drives the power wheel module according to the voltage control signal.

Abstract: A field effect transistor includes a source region and a drain region embedded in a portion of a semiconductor substrate; a gate dielectric overlying a channel region located between the source region and the drain region; a gate electrode overlying the gate dielectric; a dielectric gate liner laterally surrounding the gate electrode; a inner gate spacer laterally surrounding the dielectric gate liner; a contoured gate capping dielectric including a vertically-extending portion that laterally surrounds the inner gate spacer and a horizontally-extending portion that overlies the gate electrode; and a outer gate spacer laterally surrounding the contoured gate capping dielectric.

Abstract: An information handling system may include an information handling resource and a liquid cooling system for providing cooling of the information handling resource. The liquid cooling system may include a pump configured to drive flow of a liquid coolant through the liquid cooling system, a pump speed sensor configured to generate a pump speed signal indicative of a speed associated with the pump, and a processing device configured to receive the pump speed signal, determine whether the speed exceeds a threshold pump speed, and if the speed exceeds the threshold pump speed, take one or more remedial actions.

Abstract: A method includes bonding a first package component on a composite carrier, and performing a first polishing process on the composite carrier to remove a base carrier of the composite carrier. The first polishing process stops on a first layer of the composite carrier. A second polishing process is performed to remove the first layer of the composite carrier. The second polishing process stops on a second layer of the composite carrier. A third polishing process is performed to remove a plurality of layers in the composite carrier. The plurality of layers include the second layer, and the third polishing process stops on a dielectric layer in the first package component.

Abstract: A method of forming a transducer includes depositing a first dielectric layer on a first electrode, patterning the first dielectric layer to form a plurality of first protrusions in a first region and a plurality of second protrusions in a second region, where a density of the plurality of first protrusions in the first region is different from a density of the plurality of second protrusions in the second region, and bonding the first dielectric layer to a second electrode using a second dielectric layer, where sidewalls of the second dielectric layer define a cavity disposed between the first electrode and the second electrode, and where the plurality of first protrusions and the plurality of second protrusions are disposed in the cavity.

Abstract: The present invention provides a flash memory controller configured to access a flash memory module. The flash memory controller includes a transmission interface circuit, a buffer memory and a microprocessor. The transmission interface circuit is coupled to a host device, and the transmission interface circuit includes a time queue, at least one virtual queue and a command processing circuit, wherein the command processing circuit is configured to receive a plurality commands from a host device, write information of the plurality of commands into the time queue in sequence, and write the information of at least part of the plurality of commands into the at least one virtual queue. The buffer memory is configured to store the plurality of commands. The microprocessor is configured to selectively read the time queue or the at least one virtual queue to read the information of the plurality of commands.

Abstract: A transistor includes a gate structure, a spacer laterally surrounding the gate structure. a channel layer underlying the gate structure and comprising a two-dimensional (2D) material, and a source/drain contact laterally separated from the gate structure by the spacer and laterally coupled to the channel layer.

Abstract: A furniture assembly includes a first object, a second object, a self-closing device, an aiding member, an interlock mechanism and an actuating part. The second object is displaceable relative to the first object. The self-closing device is arranged on the first object and includes a base, a working member and a resilient member. The working member and the aiding member are movable relative to the base. The interlock mechanism is arranged on the first object. The actuating part is arranged on the second object. When the second object is located at the extended position and the working member returns to an initial position from an engaging position in response to a self-closing resilient force provided by the resilient member, the aiding member is located at a predetermined position to retain at least one locking member of the interlock mechanism at a locking position.

Abstract: The main objective of the present invention is to provide a lactic acid bacterial strain and a composition for improving gut microbiota composition. The composition comprises the lactic acid bacterial strain and/or extracellular vesicles secreted by the lactic acid bacterial strain. Another objective of the present invention is to provide a method for improving gut microbiota composition and products of the lactic acid bacterial strain. Additionally, the composition of the present invention has the capability to influence the growth of Firmicutes and Bacteroidetes, thereby leading to an improvement in gut microbiota composition.

Abstract: In some embodiments, portions of a pattern, generated in a layout process, of a layer in an integrated circuit, such as those of a layer of metallic power lines in a power grid (PG), are removed after the layout process through a computer-implemented process analogous to solving the N-coloring problem. Through this post-processing removal process, pattern portions can be removed so as reduce the coverage of the layer in the fabricated integrated circuit to a desired extent without producing certain harmful effects, such as severing a powerline.

Abstract: The present application discloses compounds of Formula (I): (I), or pharmaceutically acceptable salt thereof, wherein R1, R2, R3, and R4 are defined in the specification, as well as methods of making and using the compounds disclosed herein for treating or ameliorating an IL-17 mediated syndrome, disorder and/or disease.

Abstract: A bridge device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller includes a second transmission interface. The first transmission interface and the second transmission interface are flash memory interfaces. In a program mode, the first transmission interface receives a first command from the second transmission interface and obtains first transfer data from a bus in response to the first command. A value of the first command is optionally set to a first value or a second value. The first value indicates a memory command transfer operation in a first direction and the second value indicates a memory data transfer operation in the first direction. The first transmission interface processes the first transfer data according to the value of the first command to obtain a memory command or written data.

Abstract: An ADC receives a first input signal and a second input signal and outputs a digital signal. The first input signal is a common-mode voltage plus a voltage difference, and the second input signal is the common-mode voltage minus the voltage difference. The ADC includes a voltage conversion circuit and multiple comparators. The voltage conversion circuit generates an intermediate voltage according to the first input signal, the second input signal, and the common-mode voltage. The comparators compare the intermediate voltage with N times a reference voltage, where N is greater than or equal to negative one and less than or equal to one. The intermediate voltage is the common-mode voltage plus or minus M times the voltage difference, where M is two to the power of R, and R is a positive integer.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: An extreme ultraviolet (EUV) photolithography system detects debris travelling from an EUV generation chamber to a scanner. The photolithography system includes a detection light source and a sensor. The detection light source outputs a detection light across a path of travel of debris particles from the EUV generation chamber. The sensor senses debris particles by detecting interaction of the debris particles with the detection light.