Patents by Inventor An Steegen
An Steegen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7928443Abstract: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.Type: GrantFiled: January 11, 2010Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: An L. Steegen, Haining S. Yang, Ying Zhang
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Patent number: 7923786Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.Type: GrantFiled: October 12, 2007Date of Patent: April 12, 2011Assignee: International Business Machines CorporationInventors: An L. Steegen, Maheswaran Surendra, Hsing-Jen Wann, Ying Zhang, Franz Zach, Robert Wong
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Publication number: 20100109048Abstract: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.Type: ApplicationFiled: January 11, 2010Publication date: May 6, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: An L. STEEGEN, Haining S. YANG, Ying ZHANG
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Patent number: 7700951Abstract: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.Type: GrantFiled: July 15, 2008Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: An L. Steegen, Haining S. Yang, Ying Zhang
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Patent number: 7655557Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: GrantFiled: June 24, 2008Date of Patent: February 2, 2010Assignee: International Business Machines CorporationInventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
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Patent number: 7550338Abstract: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.Type: GrantFiled: September 13, 2007Date of Patent: June 23, 2009Assignee: International Business Machines CorporationInventors: An L. Steegen, Haining S. Yang, Ying Zhang
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Publication number: 20080283824Abstract: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.Type: ApplicationFiled: July 15, 2008Publication date: November 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION,Inventors: An L. STEEGEN, Haining S. Yang, Ying Zhang
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Publication number: 20080254622Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: ApplicationFiled: June 24, 2008Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
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Patent number: 7429752Abstract: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.Type: GrantFiled: September 22, 2006Date of Patent: September 30, 2008Assignee: International Business Machines CorporationInventors: An L Steegen, Haining S. Yang, Ying Zhang
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Patent number: 7411227Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: GrantFiled: April 19, 2006Date of Patent: August 12, 2008Assignee: International Business Machines CorporationInventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
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Patent number: 7396714Abstract: A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.Type: GrantFiled: June 18, 2007Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Huajie Chen, Dureseti Chidambarrao, Oleg G. Gluschenkov, An L. Steegen, Haining S. Yang
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Publication number: 20080029818Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.Type: ApplicationFiled: October 12, 2007Publication date: February 7, 2008Inventors: An Steegen, Maheswaran Surendra, Hsing-Jen Wann, Ying Zhang, Franz Zach, Robert Wong
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Patent number: 7326983Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.Type: GrantFiled: March 17, 2005Date of Patent: February 5, 2008Assignee: International Business Machines CorporationInventors: An L. Steegen, Maheswaran Surendra, Hsing-Jen Wann, Ying Zhang, Franz Zach, Robert Wong
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Patent number: 7326610Abstract: Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds.Type: GrantFiled: November 10, 2005Date of Patent: February 5, 2008Assignee: International Business Machines CorporationInventors: Ricky S. Amos, Douglas A. Buchanan, Cyril Cabral, Jr., Evgeni P. Gousev, Victor Ku, An Steegen
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Publication number: 20080003735Abstract: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.Type: ApplicationFiled: September 13, 2007Publication date: January 3, 2008Applicant: International Business Machines CorporationInventors: An STEEGEN, Haining Yang, Ying Zhang
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Patent number: 7291528Abstract: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.Type: GrantFiled: March 16, 2005Date of Patent: November 6, 2007Assignee: International Business Machines CorporationInventors: Huajie Chen, Dureseti Chidambarrao, Oleg G. Gluschenkov, An L. Steegen, Haining S. Yang
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Publication number: 20070249114Abstract: A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.Type: ApplicationFiled: June 18, 2007Publication date: October 25, 2007Inventors: Huajie Chen, Dureseti Chidambarrao, Oleg Gluschenkov, An Steegen, Haining Yang
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Patent number: 7129126Abstract: A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate and forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate. The method further involves growing a strain layer in at least a portion of the gap in the semiconductor substrate. For the n-type device, the strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.Type: GrantFiled: November 5, 2003Date of Patent: October 31, 2006Assignee: International Business Machines CorporationInventors: An L. Steegen, Haining S. Yang, Ying Zhang
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Patent number: 7112481Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.Type: GrantFiled: October 20, 2005Date of Patent: September 26, 2006Assignee: International Business Machines CorporationInventors: Sunfei Fang, Cyril Cabral, Jr., Chester T. Dziobkowski, John J. Ellis-Monaghan, Christian Lavoie, Zhijiong Luo, James S. Nakos, An L. Steegen, Clement H. Wann
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Publication number: 20060189061Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: ApplicationFiled: April 19, 2006Publication date: August 24, 2006Inventors: Ricky Amos, Diane Boyd, Cyril Cabral, Richard Kaplan, Jakub Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda Mocuta, Vijay Narayanan, An Steegen, Maheswaren Surendra