Patents by Inventor An-Ting Hsiao

An-Ting Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240379796
    Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Yen-Ju Chen, Chun-Chih Cheng, Wei-Chen Hsiao
  • Publication number: 20240331200
    Abstract: An endoscope device, an endoscopic medical assistance system and an endoscopic image processing method are provided. An endoscope in the endoscope device and the endoscopic medical assistance system senses light beams reflected by an object to generate initial images. After the initial images are aligned with each other to form a superimposed image, an image fusion device of the endoscopic medical assistance system analyzes features of the superimposed image to convert the superimposed image into a feature image. The image fusion device adjusts a color depth of each of a plurality of pixel points of the feature image according to a relationship between the color depth of each of the pixel points and a maximum color depth that are classified in the same color tone in each of pixel regions of the feature image. The image fusion device generates a fusion image according to the adjusted feature image.
    Type: Application
    Filed: May 28, 2023
    Publication date: October 3, 2024
    Inventors: Yuan-Ting Fang, Ming-Huang Hsiao
  • Patent number: 12107336
    Abstract: A broadband linear polarization antenna structure, including a reference conductive layer, a first patch antenna, a second patch antenna, and a feeding portion, is provided. The reference conductive layer includes through holes. A first short pin is connected between the reference conductive layer and the first patch antenna, and a second short pin is connected between the first patch antenna and the second patch antenna. Each feeding portion penetrates the reference conductive layer through the through hole and is coupled to the first patch antenna.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: October 1, 2024
    Assignee: TMY Technology Inc.
    Inventors: Yang Tai, Shun-Chung Kuo, Wen-Tsai Tsai, An-Ting Hsiao, Wei-Yang Chen, Jiun-Wei Wu
  • Publication number: 20240316548
    Abstract: Disclosed are a semiconductor sensing chip and a microfluidic sensing system. The microfluidics sensing system includes a first inlet and a second inlet, a fluidic structure, and a semiconductor sensing chip. The first inlet and the second inlet are respectively configured for injection of a sample and a reagent. The fluidic structure is coupled to the first inlet and the second inlet. The fluidic structure is configured to mix the sample and the reagent to generate a biofluid under test. The semiconductor sensing chip is disposed at the end of the fluidic structure and configured to sense the biofluidic under test and generate a concentration sensing result corresponding to the sample.
    Type: Application
    Filed: March 22, 2024
    Publication date: September 26, 2024
    Applicant: National Taiwan University
    Inventors: Jun-Chau Chien, Shu-Yan Chuang, Yan-Ting Hsiao, Hung-Yu Hou, Yun-Chun Su
  • Patent number: 12094948
    Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Yen-Ju Chen, Chun-Chih Cheng, Wei-Chen Hsiao
  • Patent number: 12096635
    Abstract: An SONOS memory cell includes a silicon substrate. A tunnel silicon oxide layer, a silicon nitride layer and a silicon oxide layer are disposed from bottom to top on the silicon substrate. The silicon oxide layer includes two first silicon oxide layers and a second silicon oxide layer. A thickness of the silicon oxide layer is smaller than a thickness of each of the first silicon oxide layers. A control gate covers and contacts the silicon oxide layer. A first source/drain doping region and a second source/drain doping region are respectively disposed at two sides of the control gate. The silicon oxide layer has a cross section. The second silicon oxide layer is sandwiched between the two first silicon oxide layers on the cross section.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: September 17, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yung-Ting Chen, Hsueh-Chun Hsiao
  • Patent number: 12091454
    Abstract: A humanized anti-neurotensin receptor 1 (NTSR1) antibody or an antigen-binding fragment thereof. Also, a method for treating, prophylactic treating and/or preventing diseases and/or disorders caused by or related to NTSR1 activity and/or signaling, and a method or kit for detecting NTSR1 in a sample.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: September 17, 2024
    Assignees: DEVELOPMENT CENTER FOR BIOTECHNOLOGY, NATIONAL HEALTH RESEARCH INSTITUTES
    Inventors: Cheng-Chou Yu, Shu-Ping Yeh, Chao-Yang Huang, Szu-Liang Lai, Shih-Liang Hsiao, Mei-Ling Hou, Tzung-Jie Yang, Wei-Ting Sun, Liang-Yu Hsia, Andrew Yueh, Chiung-Tong Chen, Ren-Huang Wu, Pei-Shan Wu, Han-Shu Hu, Tzu-Chin Wu, Jia-Ni Tian
  • Publication number: 20240281652
    Abstract: A training method and training system for neural network model. The training method includes: (a) receiving image data; (b) preforming first-tier calculation including first convolution and first non-linear calculation; (c) performing combination computation; (d) performing second-tier calculation based on output of the combination computation when it is determined to execute, and it includes second convolution and second non-linear calculation; and (e) when the second-tier calculation is determined not to execute, classifying the output of the combination computation. Step (c) includes: (c1) grouping output of the first-tier calculation; (c2) performing linear and non-linear computation respectively on different groups of the output of the first-tier calculation; and (c3) performing consolidate computation based on output of the linear and the non-linear computation.
    Type: Application
    Filed: June 2, 2023
    Publication date: August 22, 2024
    Inventors: YI-TA WU, KUANG-TING HSIAO, FU-CHIEH CHANG
  • Patent number: 12040607
    Abstract: A voltage stabilizer is provided for stabilizing a gate-source voltage of a switching element, wherein a source of the switching element receives a first driving voltage. The voltage stabilizer includes a transistor and a first resistor. A base of the transistor receives a second driving voltage, a collector of the bipolar junction transistor is electrically connected to a gate of the switching element, a first terminal of the first resistor is electrically connected to the collector and the gate, a second terminal of the first resistor is electrically connected to the source of the switching element and receives the first driving voltage.
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: July 16, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Kuan-Ting Lee, Chen-Chieh Kao, Yu-Liang Lin, Cheng-Chia Hsiao
  • Publication number: 20240233564
    Abstract: A communication method in a virtual environment includes initiating, by a first user, a virtual classroom through an education Metaverse application program of a first user device; attending, by at least a second user, the virtual classroom through an education Metaverse application program of a second user device; activating, by the first user, a class teaching mode, such that the first user and at least the second user login a cloud streaming system through corresponding education Metaverse application program of the first user device and the second user device to represent a first Avatar and a second Avatar for communication in the virtual classroom; wherein the virtual classroom is configured to render a spatial audio in a three-dimensional (3D) space.
    Type: Application
    Filed: September 22, 2023
    Publication date: July 11, 2024
    Applicant: ViewSonic International Corporation
    Inventors: Ting-Ting Hsiao, Chih-Wei Lu, Po-Chun Hsu, Wen-Ju Chow, Shih-Chang Weng, Yun-Cheng Hsin, Yu-Zhen Huang
  • Publication number: 20240186235
    Abstract: An integrated chip including a substrate and a transistor device along the substrate. A plurality of conductive interconnects are over the transistor device. A first under-bump metal (UBM) layer is over the conductive interconnects. A first metal bump is directly over the first UBM layer. A metal-insulator-metal (MIM) capacitor array is over the transistor device and under the first UBM layer. The MIM capacitor array includes a first MIM capacitor and a second MIM capacitor coupled in parallel and disposed directly under the first UBM layer.
    Type: Application
    Filed: January 5, 2023
    Publication date: June 6, 2024
    Inventors: Shu-Cheng Chin, Kong-Beng Thei, Jung-Hui Kao, Wen-Ting Hsiao, Kuei-Kai Hou
  • Publication number: 20240178572
    Abstract: A slot antenna structure includes a metal trough and two metal plates. The metal trough includes a metal bottom plate, two metal sidewalls erected on two opposite long sides of the metal bottom plate respectively, two metal closing walls erected on two opposite short sides of the metal bottom plate respectively, and an opening formed and surrounded by the metal sidewalls and the metal closing walls. The metal plates are provided on the opening. A slot is formed between the metal plates and extends in a straight line to separate the metal plates. An electrical unit is provided on the metal plates and astride the slot. The metal plates and the metal trough form a resonance chamber in communication with the slot. The depth from the opening to the inner bottom side of the metal trough is generally one eighth of the wavelength of an input signal.
    Type: Application
    Filed: August 25, 2023
    Publication date: May 30, 2024
    Inventor: Yu-Ting HSIAO
  • Publication number: 20240149541
    Abstract: A process for continuous production of z-threaded fiber reinforced polymer composites. The process includes providing a pre-formed fiber fabric including a plurality of fibers and a pre-formed, solidified film having a film thickness dimension, wherein the film includes a heat-meltable base matrix material in combination with a plurality of z-aligned nanofibers disposed within the base matrix material. The film and fiber fabric are advanced in layered relation through a constricting matrix transfer station, wherein the fiber fabric is heated to a temperature at or above the melting point of the base matrix material and the base matrix material progressively melts at an interface with the fabric face and flows with the nanofibers into the fiber fabric in the fabric thickness dimension as the film and fiber fabric move through the matrix transfer station.
    Type: Application
    Filed: April 14, 2022
    Publication date: May 9, 2024
    Inventors: KUANG-TING HSIAO, SEBASTIAN KIRMSE
  • Publication number: 20240049019
    Abstract: Wireless local area network (WLAN) device testing that includes acquiring a data flow feature value used in testing a WLAN device, generating a WLAN simulation environment based on an interference environment index feature of the WLAN, controlling a data transmitter in the WLAN simulation environment to transmit a data packet based on the data flow feature value, acquiring a reception status of the data receiver device for the data packet, and based on the reception status of the data receiver device for the data packet, testing the network performance in the simulation environment.
    Type: Application
    Filed: October 20, 2023
    Publication date: February 8, 2024
    Applicant: Tencent Technology (Shenzhen) Company Limited
    Inventors: Wei-Ting HSIAO, Zhen-Xing WEN, Honghao LIU
  • Patent number: D1012931
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: January 30, 2024
    Assignee: HTC CORPORATION
    Inventors: Wei-Ting Hsiao, Yien-Chun Kuo, Meng-Sheng Chiang
  • Patent number: D1013687
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: February 6, 2024
    Assignee: HTC Corporation
    Inventors: Wei-Ting Hsiao, Zhi-Qing Wu, Tse-Hsun Pang, Yien-Chun Kuo, Meng-Sheng Chiang
  • Patent number: D1027444
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: May 21, 2024
    Assignee: HTC CORPORATION
    Inventors: Wei-Ting Hsiao, Yien-Chun Kuo
  • Patent number: D1033431
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: July 2, 2024
    Assignee: HTC Corporation
    Inventors: Wei-Ting Hsiao, Yien-Chun Kuo
  • Patent number: D1040514
    Type: Grant
    Filed: July 11, 2023
    Date of Patent: September 3, 2024
    Assignee: HTC Corporation
    Inventors: Wei-Ting Hsiao, Yien-Chun Kuo
  • Patent number: D1040806
    Type: Grant
    Filed: August 14, 2023
    Date of Patent: September 3, 2024
    Assignee: HTC Corporation
    Inventors: Wei-Ting Hsiao, Zhi-Qing Wu, Tse-Hsun Pang, Yien-Chun Kuo, Meng-Sheng Chiang