Patents by Inventor An-Ting Lee
An-Ting Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996633Abstract: A wearable device includes a ground element, a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, and a fifth radiation element. The first radiation element has a feeding point, and is coupled to a first grounding point on the ground element. A slot region is surrounded by the first radiation element and the ground element. The second radiation element is coupled to a second grounding point on the ground element. The third radiation element is coupled to the second grounding point. The third radiation element and the second radiation element substantially extend in opposite directions. The fourth radiation element and the fifth radiation element are disposed inside the slot region. An antenna structure is formed by the first radiation element, the second radiation element, the third radiation element, the fourth radiation element, and the fifth radiation element.Type: GrantFiled: September 6, 2022Date of Patent: May 28, 2024Assignee: QUANTA COMPUTER INC.Inventors: Chun-I Cheng, Chung-Ting Hung, Chin-Lung Tsai, Kuan-Hsien Lee, Yu-Chen Zhao, Kai-Hsiang Chang
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Patent number: 11996630Abstract: An antenna structure includes a ground element, a first radiation element, a second radiation element, a third radiation element, and a nonconductive support element. The first radiation element is coupled to a first grounding point on the ground element. The second radiation element has a feeding point. The second radiation element is adjacent to the first radiation element. The third radiation element is coupled to a second grounding point on the ground element. The third radiation element is adjacent to the second radiation element. The first radiation element, the second radiation element, and the third radiation element are disposed on the nonconductive support element. The second radiation element is at least partially surrounded by the first radiation element. The third radiation element is at least partially surrounded by the second radiation element.Type: GrantFiled: September 2, 2022Date of Patent: May 28, 2024Assignee: QUANTA COMPUTER INC.Inventors: Yu-Chen Zhao, Chung-Ting Hung, Chin-Lung Tsai, Ying-Cong Deng, Kuan-Hsien Lee, Yi-Chih Lo, Kai-Hsiang Chang, Chun-I Cheng, Yan-Cheng Huang
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Publication number: 20240168326Abstract: The present disclosure provides a display panel and a manufacturing method therefor, and a display apparatus, which relate to the technical field of displaying. The display panel includes a first base plate and a second base plate which are aligned with each other; the first base plate includes a first substrate and a thin film transistor; the thin film transistor includes an active layer; an optical adjustment layer is disposed on the second base plate; an orthographic projection of the optical adjustment layer on the first substrate overlaps with an orthographic projection of the active layer on the first substrate. That is, the optical adjustment layer corresponds to the active layer. In a laminating direction of the display panel, the existence of the optical adjustment layer with a certain height enables a reflecting surface of the second base plate to be closer to the first base plate.Type: ApplicationFiled: September 17, 2021Publication date: May 23, 2024Applicants: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Yingying Qu, Lingdan Bo, Ting Dong, Jianhua Huang, Qiujie Su, Dongchuan Chen, Yanping Liao, Seungmin Lee, Jiantao Liu, Yue Yang
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Patent number: 11987431Abstract: A top-opening substrate carrier comprises a container body, a door member and at least one latching mechanism. The latching mechanism includes a rotary drive member, a first driven cam, a second driven cam, a first connecting rod, a second connecting rod, two longitudinal latching arms and two lateral latching arms. The first driven cam and the second driven cam are disposed at two sides of the rotary drive member. When the rotary drive member is rotated by force, it links and activates the first connecting rod and the second connecting rod to synchronously drive the first driven cam and the second driven cam to rotate, thereby driving the two longitudinal latching arms and the two lateral latching arms to project towards locking holes of the container body and locked, or retract from the locking holes of the container body and unlocked.Type: GrantFiled: March 27, 2023Date of Patent: May 21, 2024Assignee: GUDENG PRECISION INDUSTRIAL CO., LTD.Inventors: Ming-Chien Chiu, Yung-Chin Pan, Cheng-En Chung, Chih-Ming Lin, Po-Ting Lee, Wei-Chien Liu, Tzu-Ning Huang
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Patent number: 11990291Abstract: A multiple function button for an information handling system includes an outer shell and an inner button. The outer shell includes multiple channels having first, second, third and fourth channels. The inner button is inserted within the outer shell. The inner button includes a tab and a contact component. The tab moves within the multiple channels. When the tab is within the first channel, the inner button is in a first position and contact component is positioned over a first contact of the information handling system. When the tab is within the third channel, the inner button is in a second position and the contact component is positioned over a second contact of the information handling system.Type: GrantFiled: May 26, 2022Date of Patent: May 21, 2024Assignee: Dell Products L.P.Inventors: Jer-Yo Lee, Chun-Ting Lu, Cheng-Hsiang Chuang
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Publication number: 20240164099Abstract: An integrated circuit structure includes a substrate, semiconductor devices, an inter-layer dielectric (ILD) structure, an interconnect, a dielectric layer, an etching barrier layer, a conductive layer, and memory units. The semiconductor devices are on the substrate. The ILD structure is over the semiconductor devices. The interconnect is in the ILD structure and electrically connected to the semiconductor devices. The dielectric layer is over the ILD structure. The etching barrier layer is on the first dielectric layer. The conductive layer is on the etching barrier layer. The memory units are stacked in a vertical direction over the etching barrier layer.Type: ApplicationFiled: March 15, 2023Publication date: May 16, 2024Inventors: Hong-Ji LEE, Tzung-Ting HAN, Chang-Wen JIAN
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Publication number: 20240162082Abstract: A manufacturing method of a semiconductor structure including following steps is provided. A first sacrificial layer and a second sacrificial layer are formed in a first substrate. A first device layer including a first dielectric structure and a first landing pad is formed on the first substrate. A second device layer including a second dielectric structure and a second landing pad is formed on a second substrate. The first dielectric structure is bonded to the second dielectric structure. A portion of the first substrate is removed to expose the first sacrificial layer and the second sacrificial layer. An etch-back process is performed by using the first substrate as a mask to form a first opening exposing the first landing pad and a second opening exposing the second landing pad. A first TSV structure and a second TSV structure are respectively formed in the first opening and the second opening.Type: ApplicationFiled: January 6, 2023Publication date: May 16, 2024Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Shyng-Yeuan Che, Ya-Ting Chen, Pin-Chieh Huang
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Patent number: 11984410Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.Type: GrantFiled: May 5, 2023Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wan-Yu Lee, Chiang Lin, Yueh-Ting Lin, Hua-Wei Tseng, Li-Hsien Huang, Yu-Hsiang Hu
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Patent number: 11984489Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.Type: GrantFiled: November 21, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Hsiu Liu, Feng-Cheng Yang, Tsung-Lin Lee, Wei-Yang Lee, Yen-Ming Chen, Yen-Ting Chen
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Patent number: 11984499Abstract: A trench silicon carbide metal-oxide semiconductor field effect transistor includes a silicon carbide semiconductor substrate and a trench metal-oxide semiconductor field effect transistor, the field effect transistor includes a trench vertically arranged and penetrating along a first horizontal direction, a gate insulating layer formed on an inner wall of the trench, a first poly gate formed on the gate insulating layer, a shield region formed outsides and below the trench, and a field plate arranged between a bottom wall of the trench and the shield region, and the field plate has semiconductor doping and is laterally in contact to a current spreading layer to deplete electrons of the current spreading layer when a reverse bias voltage is applied.Type: GrantFiled: January 11, 2021Date of Patent: May 14, 2024Assignee: SHANGHAI HESTIA POWER INC.Inventors: Chien-Chung Hung, Kuo-Ting Chu, Lurng-Shehng Lee, Chwan-Yin Li
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Patent number: 11984485Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.Type: GrantFiled: March 3, 2022Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hsien Cheng, Jr-Hung Li, Tai-Chun Huang, Tze-Liang Lee, Chung-Ting Ko, Jr-Yu Chen, Wan-Chen Hsieh
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Patent number: 11985822Abstract: A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.Type: GrantFiled: September 2, 2020Date of Patent: May 14, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Teng-Hao Yeh, Chih-Wei Hu, Hang-Ting Lue, Guan-Ru Lee
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Publication number: 20240153993Abstract: Semiconductor devices and methods of fabrication are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin and into a substrate as an initial step in forming a source/drain region. A first semiconductor material is epitaxially grown from channels exposed along sidewalls of the opening to form first source/drain structures. A second semiconductor material is epitaxially grown from the first semiconductor material to form a second source/drain structure over and to fill a space between the first source/drain structures. A bottom of the second source/drain structure is located below a bottommost surface of the first source/drain structures. The second semiconductor material has a greater concentration percentage by volume of germanium than the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Inventors: Yen-Ting Chen, Po-Shao Lin, Wei-Yang Lee
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Publication number: 20240154629Abstract: A 24 GHz band-pass filter includes a step impedance resonator, a first U-shape feeding portion, a second U-shape feeding portion, short-circuit stubs and open-circuit stubs. The step impedance resonator includes a first main portion, a second main portion, and a connection portion for connecting the main portions to each other. The first main portion and the second main portion are electrically connected to a first signal input/output port and a second signal input/output port. The first U-shape feeding portion is electrically connected between the first main portion and the first signal input/output port. The second U-shape feeding portion is electrically connected between the second main portion and the second signal input/output port. The short-circuit stubs are electrically connected to coupling segments of the step impedance resonator. The open-circuit stubs are electrically connected to the first U-shape feeding portion and the second U-shape feeding portion.Type: ApplicationFiled: November 1, 2023Publication date: May 9, 2024Inventors: Kun Yen TU, Meng-Hua TSAI, Wei Ting LEE, Sin-Siang WANG
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Publication number: 20240154447Abstract: A power system including a first battery pack, a second battery pack, and a power management circuit is disclosed. The first battery pack has a first end and a second end, and has a first battery capacity. The second battery pack has a third end and a fourth end. The third end is coupled to the second end of the first battery pack and provides a low battery voltage. The fourth end is grounded, the second battery pack has a second battery capacity, and the second battery capacity is greater than the first battery capacity. The power management circuit is coupled to the second battery pack to receive the low battery voltage, and provides a component operating voltage to an electronic components based on the low battery voltage.Type: ApplicationFiled: August 29, 2023Publication date: May 9, 2024Applicant: PEGATRON CORPORATIONInventors: Yi-Hsuan Lee, Liang-Cheng Kuo, Chun-Wei Ko, Ya Ju Cheng, Chih Wei Huang, Ywh Woei Yeh, Yu Cheng Lin, Yen Ting Wang
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Publication number: 20240138723Abstract: A test strip for sampling a bodily fluid may include multiple layers of a substrate material, an adhesive between at least some of the multiple layers, and a microfluidic channel formed between at least some of the multiple layers. The test strip may further include multiple electrodes on one of the multiple layers, positioned and partially exposed within the microfluidic channel, an additional material positioned at or near an entrance to the microfluidic channel, to selectively limit the flow of at least one of bubbles or debris into the microfluidic channel, and at least one exit port in at least one of the multiple layers to allow for release of pressure from the test strip. In some embodiments, the test strip is a saliva analysis test strip. In some embodiments, the test strip includes multiple exit ports to prevent blockage of sample flow.Type: ApplicationFiled: May 31, 2023Publication date: May 2, 2024Inventors: Thanh Cong Nguyen, Efstratios Skafidas, Duc Hau Huynh, Michael Erlichster, Duc Phuong Nguyen, Hsien Ming, Gursharan Chana, Ting Ting Lee, Chathurika Darshani Abeyrathne, You Liang, Trevor John Kilpatrick, Michael Luther, Alan Dayvault Luther
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Publication number: 20240142679Abstract: An absorber and a method of forming an absorber. The absorber may include a semiconductor absorption structure doped with dopants of a first conductivity type. The absorber may also include a semiconductor substrate doped with dopants of a second conductivity type different from the first conductivity type. The absorber may further include a dielectric layer between the semiconductor absorption structure and the semiconductor substrate. The absorber may additionally include a buried semiconductor structure included in a cavity of the dielectric layer, the buried semiconductor structure doped with dopants of the first conductivity type.Type: ApplicationFiled: March 4, 2021Publication date: May 2, 2024Inventors: Conglin Sun, Chong Pei Ho, Lennon Yao Ting Lee
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Publication number: 20240142303Abstract: An integrated circuit spectrometer comprises a photonic circuit comprising: an optical input port for receiving light from a light source: and a filter array of filter elements, such as microring resonators, in optical communication with the optical input port. Each microring resonator is characterized by a different series of resonance wavelengths. If alternative filter elements are used, the filter elements may have different filter peaks to each other. The integrated circuit spectrometer also comprises a plurality of detectors, each of which is associated with one of said microring resonators to detect photons from an output of the microring resonator: and at least one processor configured to reconstruct, from signals received at the detectors, an input spectrum of the light received at the optical input port. The input spectrum may be reconstructed by an artificial neural network.Type: ApplicationFiled: March 17, 2021Publication date: May 2, 2024Inventors: Anmin KONG, Shaonan ZHENG, Lennon Yao Ting LEE
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Patent number: 11973449Abstract: A motor system includes a driving circuit, a motor device and a control circuit. The driving circuit outputs a driving current according to multiple control signals. The motor device drives a rotor unit to rotate according to the driving current, and includes a first sensor and a second sensor to sense the polarity of the rotor unit in different directions to generate polarity data. The control circuit receives the polarity data. When the polarity data is in a first state, the control circuit records a first maintenance time. When the polarity data changes from the first state to a second state, and a second maintenance time for the second state corresponds to the first maintenance time, the control circuit sets the polarity data to a third state, until the polarity data is changed from the third state to a fourth state.Type: GrantFiled: November 24, 2021Date of Patent: April 30, 2024Assignee: Sentelic CorporationInventor: Wen-Ting Lee
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Publication number: 20240137778Abstract: Provided is a signal forwarding method and related apparatus. In the method, a repeater determines which part of received signals, which are the cellular communication signals, are to be forwarded, according to a control of the network, and then utilizes a gain of the repeater to amplify the determined signals and forwarding the amplified signals. With this method, the effective power spectrum density transmitted by the repeater becomes larger. Multipath or multi-user interference may also be minimized.Type: ApplicationFiled: October 23, 2023Publication date: April 25, 2024Applicant: Morelink Technology CorporationInventors: Chunn-yenn LIN, Yung-ting LEE