Abstract: A semiconductor device structure is provided. The structure includes a substrate and a data storage element over the substrate. The structure also includes a protective element extending into the data storage element. A bottom surface of the protective element is between a top surface of the data storage element and a bottom surface of the data storage element. The structure further includes a first electrode electrically connected to the data storage element and a second electrode electrically connected to the data storage element.

Abstract: A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of AxB1?xO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.

Abstract: An adjustable airway securement device that protects and enables placement, and positional stability of airway devices or endotracheal tube apparatus (ETT) of different lengths and diameters adapted to fit the airways of patients having oral and tracheal anatomical structures and facial geometries of various sizes. An internal force-exerting member, such as a flexible beam member operatively connected to an Interlock, collar, or a bonding material, or a surface texturing structure is urged into securing engagement with a sidewall of an airway device in response to rotational closure of a securing apparatus or a clamshell-type clamping member. The clamping member is configured to interact in clamping engagement with the continuous sidewall of the airway device via the Interlock device adjustably positioned in the stabilization system to prevent clinically significant movement of the distal end of the airway device with respect to the vocal cords of the patient.

Abstract: Disclosed are example methods, systems, and devices that allow for the generation and provisioning of digital credentials, which may demonstrate that a trusted entity has validated individual identity attributes, or sets of attributes, of a user. Digital credentials may also demonstrate one or more extrapolations resulting from deductions or inductions from validated identity attributes. A receiver device may indicate which identity attributes or extrapolations are sought by displaying a QR or other code and/or via a transmission using NFC or other wireless communication, and a user device may access corresponding digital attributes in an ID wallet to be provisioned via code or transmission. Digital credentials may restrict uses and usability of identity attributes. Cryptographic keys and/or distributed ledger records may allow recipients to verify authenticity of digital credentials. The same identity attribute may be proven by showing validation by multiple selectable trusted entities.

Abstract: Systems, methods and computer-readable storage media utilized to track a plurality of assets on a distributed ledger network. One method includes receiving, by an asset issuer computing device, a request to track a specific asset on the distributed ledger network. The method further includes determining, by the asset issuer computing device, an asset type associated with the specific asset. The method further includes generating, by the asset issuer computing device, a unique identifier identifying the specific asset. The method further includes generating, by the asset issuer computing device, a unique tracking identifier, the unique tracking identifier including a subset of identifiers, the subset of identifiers including an asset issuer identifier, an asset type identifier, and the unique identifier.

Abstract: A memory device includes a field effect transistor and a variable-capacitance capacitor. A gate structure includes a gate dielectric and an intermediate electrode. The variable-capacitance capacitor includes a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable-capacitance node dielectric and including an electrical-field-programmable metal oxide material. The electrical-field-programmable metal oxide material provides a variable effective dielectric constant, and a data bit may be stored as a dielectric state of the variable-capacitance node dielectric in the memory device. The variable-capacitance node dielectric provides reversible electrical field-dependent resistivity modulation, or reversible electrical field-dependent movement of metal atoms therein.

Abstract: Systems and methods for property valuation using automated valuation models are described herein, which involve a complex series of workflows for data processing, automated valuation modeling, and error detection—each of which are capable of leveraging machine learning algorithms/techniques and can be combined and operated together in a specific manner in order to improve data availability and data quality, improve the accuracy of generated property value estimates, improve the performance of the models over time, and allow the property value estimation to be adapted to various use cases. Estimation of property value may involve an ensemble model which reconciles the outputs of different sub-models based on a use case, with the sub-models using different approaches that have their own strengths and weaknesses.

Abstract: Antibodies, fragments thereof, and chimeric proteins comprising same are presented that have specific binding activity against CD30. Advantageously, contemplated molecules can be used in pharmaceutical compositions for immune therapy, particularly in individuals diagnosed with hematopoietic malignancies, including Hodgkin lymphoma, CD30-positive B cell lymphomas, CD30-positive T cell lymphomas, CD30-positive NK cell lymphomas.

Abstract: Techniques for providing device functionalities using device components are described. A system receives a system-generated directive from a skill system and determines a workflow to execute. The system implements a response orchestrator that operates based on the workflow that includes interception points where cross-cutting functionalities can be invoked as pluggable components. The interception points occur pre-system-generated directive, pre-device-facing directive, post-device-facing directive generation, post-device-facing directive dispatch, and the like. The system supports asynchronous execution, conditional execution, and sequential execution of components. Data determined by the cross functionality components can be used by other components for processing.

Abstract: A recombinant Pichia pastoris strain which is genetically modified for highly expressing pediocin PA-1 and secreted into a medium so that the pediocin PA-1 is easily collected and purified from the culture medium. The obtained pediocin PA-1 has specific antimicrobial activities against Listeria monocytogenes ATCC 13932 and several other bacteria strains.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a first dielectric layer, an etching stop layer, a second dielectric layer, a conductive via, and a data storage structure. The first dielectric layer is disposed on the substrate. The etching stop layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the etching stop layer. The first dielectric layer, the etching stop layer, and the second dielectric layer collectively define an opening. The conductive via is disposed in the opening. The data storage structure is disposed on the conductive via.

Abstract: The present invention is a novel roasting pan system whereby a meat probe is configured for inserting into any product placed within the roasting pan and the temperature reading is read on the outside of the pan.

Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.

Abstract: An electronic device with a microphone, a speaker, a processor, and a power tool battery pack connectable to and powering the speaker and the processor. The electronic device has software that can cause the processor to perform operations which can cause the electronic device to operate in first and second modes. While the electronic device is operating in the first mode, the device can generate first audio data representing user speech captured by the microphone which can be analyzed by the electronic device or a remote server. The electronic device can switch from operating in the first mode to operating in a second mode, where the electronic device can receive, second audio data from another electronic device. The electronic device can then output, using the speaker, audible content represented by the second audio data.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. A first conductive structure overlies a substrate. A second conductive structure overlies the first conductive structure. A data storage structure is disposed between the first and second conductive structures. The data storage structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. Respective bandgaps of the first, second, and third dielectric layers are different from one another.

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, a method comprises programming a word or page of non-volatile memory cells in an analog neural memory system; and identifying any fast bits in the word or page of non-volatile memory cells.

Abstract: Fusion Protein compositions comprising masked IFNs and methods of making masked IFNs are disclosed herein. Consequently, the masked IFNs can be fused to a Mab or binding fragment thereof and be administered to patients as a therapeutic modality and provide a method of treating cancer, immunological disorders and other disease.

Abstract: Methods of forming a stack without damaging underlying layers are discussed. The encapsulation layer and dielectric layer are highly conformal, have low etch rates, and good hermeticity. These films may be used to protect chalcogen materials in PCRAM devices or any substrates sensitive to oxygen or moisture. Some embodiments utilize a two-step process comprising a first ALD process to form an encapsulation layer and oxidation process to form a dielectric layer.

Abstract: Numerous examples are disclosed of an artificial neural network that comprises vector-by-matrix multiplication arrays utilizing analog outputs. In one example, a system comprises a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns; and an output circuit to receive a respective neuron current from respective columns of the vector by matrix multiplication array and to generate a respective output voltage, the output circuit comprising a neuron scalar to generate a scaled current from the received respective neuron current, and a current-to-voltage converter to convert the scaled current into the respective output voltage.

Abstract: Numerous examples are disclosed of an artificial neural network comprising a plurality of reference arrays used for configuration of a vector-by-matrix multiplication array. In one example, a system comprises a vector-by-matrix multiplication array in an artificial neural network; and a plurality of reference arrays characterized by different I-V curves, wherein one or more of the plurality of reference arrays are used to generate input voltage the vector-by-matrix multiplication array during operation.