Patents by Inventor An Tsai

An Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220089625
    Abstract: Provided are organometallic compounds including a ligand LA of Formula I: Also provided are formulations including these organometallic compounds. Further provided are OLEDs and related consumer products that utilize these organometallic compounds.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 24, 2022
    Applicant: Universal Display Corporation
    Inventors: Alexey Borisovich DYATKIN, Jui-Yi TSAI, Walter YEAGER, Pierre-Luc T. BOUDREAULT, Zhiqiang JI, Bert ALLEYNE
  • Publication number: 20220093059
    Abstract: An electronic device may include an electronic display including display pixels to display an image based on compensated image data. The electronic display may also include a stressed reference pixel to exhibit burn-in related aging in response to one or more stress sessions and a non-stressed reference pixel configured to not undergo the one or more stress sessions. Additionally, the electronic device may include image processing circuitry to determine a panel-specific aging profile based on a comparison between one or more properties of the stressed reference pixel and the one or more properties of the non-stressed reference pixel. The image processing circuitry may also generate one or more gain maps based on the panel-specific aging profile and generate the compensated image data by applying the one or more gain maps to input image data.
    Type: Application
    Filed: July 14, 2021
    Publication date: March 24, 2022
    Inventors: Maofeng Yang, Jiayi Jin, David A. Doyle, Yifan Zhang, Weijun Yao, Jiye Lee, Tae-Wook Koh, Mathew K. Mathai, Chuang Qian, Tsung-Ting Tsai, James P. Landry, Kiran S. Pillai, Injae Hwang, Yongjun Li
  • Publication number: 20220093684
    Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes metal layers that are stacked over one another with dielectric layers disposed between. The metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ. A sidewall spacer surrounds an outer periphery of the top electrode. Less than an entirety of a top electrode surface is in direct electrical contact with a metal via connected to the upper metal layer.
    Type: Application
    Filed: November 23, 2021
    Publication date: March 24, 2022
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Jiunyu Tsai, Sheng-Huang Huang
  • Publication number: 20220093783
    Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed directly on the shallow recess.
    Type: Application
    Filed: December 7, 2021
    Publication date: March 24, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kuang Hsieh, Shih-Hung Tsai
  • Publication number: 20220087516
    Abstract: The endoscopic device includes a main member having a front slot and a shaft member having a spiral strip selectively running through the slot. The spiral strip is connected to a rotational element whose front end is provided with an optical element. A camera support element is extended from the main member and a camera element is supported by the camera support element. By running the spiral strip through the slot to turn the rotational element and the optical element, a viewing direction of the camera element is altered by the optical element.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Inventors: Tsang-Chou Tsai, John Huang
  • Patent number: 11282791
    Abstract: A semiconductor device includes a first chip package, a heat dissipation structure and an adapter. The first chip package includes a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die has an active surface and a back surface opposite to the active surface. The heat dissipation structure is connected to the chip package. The adapter is disposed over the first chip package and electrically connected to the semiconductor die.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hung-Yi Kuo, Hao-Yi Tsai, Tin-Hao Kuo, Yu-Chia Lai, Shih-Wei Chen
  • Patent number: 11283402
    Abstract: A device includes a sensor configured to provide a temperature-sensitive voltage and an oscillator. The sensor includes: a first transistor, being a diode-connected transistor; a second transistor coupled between a source of the first transistor and ground, wherein a gate of the second transistor is controllable by an enable signal; and a current source configured to control the first transistor and comprising a third transistor, a drain of which is directly connected to a drain of the first transistor, the third transistor being a diode-connected transistor. The oscillator includes: a digital delay cell; and an adjustment device configured to, based on the temperature-sensitive voltage, adjust a delay of the digital delay cell. The digital delay cell produces, based on the adjusted delay, a signal at an oscillation frequency.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ping-Han Tsai, Chih-Sheng Hou, Po-Yu Chen, Nan-Hsin Tseng
  • Patent number: 11283475
    Abstract: A wireless access point device includes a radio to establish a communication link on a first primary channel using a wireless local area network (WLAN) protocol. The communication link has an operating channel bandwidth and a communication link bandwidth that is adjustable to be identical to or lower than the operating channel bandwidth. The operating channel bandwidth includes the first primary channel and a plurality of secondary channels. The WAP device is to determine that received data, which contains in-phase and quadrature (I/Q) values, does not include a valid WLAN frame; determine that a first secondary channel of the plurality of secondary channels has an interference signal signature via application of frequency domain analysis on the I/Q sample values; and modify the communication link bandwidth from a first frequency range to a second width frequency range, which does not include the first secondary channel.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: March 22, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Kun Ting Tsai, Ashish Kumar Shukla
  • Patent number: 11282728
    Abstract: The present disclosure relates to a contamination controlled semiconductor processing system. The contamination controlled semiconductor processing system includes a processing chamber, a contamination detection system, and a contamination removal system. The processing chamber is configured to process a wafer. The contamination detection system is configured to determine whether a contamination level on a surface of the door is greater than a baseline level. The contamination removal system is configured to remove contaminants from the surface of the door in response to the contamination level being greater than the baseline level.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: March 22, 2022
    Inventors: Bo Chen Chen, Sheng-Wei Wu, Yung-Li Tsai
  • Patent number: 11283231
    Abstract: A clamping module is adapted to clamp a memory module and insert or remove the memory module into/from a slot. The clamping module includes a main body, two jaw clamps and a blocking pressing plate. The two jaw clamps are movably disposed on the main body and adapted to move in relative to each other to clamp or release the memory module. The blocking pressing plate is movably disposed on the main body, wherein after the two jaw clamps clamp the memory module to a position in contact with the slot, the two jaw clamps moves away from each other so that the memory module is released and the blocking pressing plate moves from a first position to a second position in order to press the memory module so that the memory module is inserted into the slot.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: March 22, 2022
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Hsing-Feng Tsai, Yen-Yun Chang, Tsung-Ta Wu
  • Patent number: 11282707
    Abstract: A method includes: receiving a first wafer; defining a first zone and a second zone on the first wafer and a plurality of first areas; defining a plurality of first areas and second areas for the first and second zones, respectively; projecting first ion beams onto the first areas and receiving first thermal waves in response to the first ion beams; rotating the first wafer by a twist angle; projecting second ion beams onto the second areas and receiving second thermal waves in response to the second ion beams; and estimating a first crystalline orientation angle of the first wafer based on the first and second ion beams and the first and second thermal waves.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Bo-Tsung Tsai
  • Patent number: 11284417
    Abstract: Certain aspects of the present disclosure provide a method for wireless communication by a base station (BS). The method generally includes receiving an indication of current remaining available transmit power from a user equipment (UE). The method further includes communicating information indicating a data rate parameter and a communication configuration to the UE. The data rate parameter is for use by the UE on an uplink with the BS. The communication configuration affects uplink transmission duty cycle on the uplink based on whether the current remaining available transmit power and a current channel state between the BS and the UE satisfy a condition. The method further includes receiving signals based on the data rate parameter and the communication configuration from the UE on the uplink.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: March 22, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Shiau-He Tsai, Raghu Narayan Challa
  • Patent number: 11284035
    Abstract: Provided is a data transmission system including analog image frame buffer, line analog-to-digital converter, line buffer memory, and an interface. First, the analog image frame buffer stores the image data lines generated from the image sensor as analog signals, and then the line analog digital converter which is electrically connected to the analog image frame buffer converts the image data lines from analog signals to digital signals. Then, the image data lines converted into digital signals are stored in one of the line buffer memories. Then, according to the user's needs, the image data line of the digital signal is temporarily stored in another line buffer memory. Finally, according to the instructions of the master device, the interface outputs the image data lines of digital signals according to the conversion order of the line analog to digital converter.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: March 22, 2022
    Assignee: Guangzhou Tyrafos Semiconductor Tech. Co., Ltd.
    Inventors: Ping-Hung Yin, Jia-Shyang Wang, Pei-Ting Tsai
  • Patent number: 11281835
    Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
  • Patent number: 11278509
    Abstract: The present invention relates to a composition comprising a lithium salt of an N-substituted glycine compound and a carrier, wherein the lithium salt of the N-substituted glycine compound is of Formula (I): in which R1, R2, and R3 each are independently hydrogen, alkyl, alkenyl, alkynyl, aralkyl, carbocyclyl, aryl, or heteroaryl, or one of R1, R2, and R3 is absent. Also provided in the present invention is a method of mitigating at least one symptom of a neuropsychiatric disorder, comprising administering to a subject in need thereof the lithium salt of an N-substituted glycine compound of Formula (I).
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: March 22, 2022
    Assignee: SyneuRx International (Taiwan) Corp.
    Inventors: Guochuan Emil Tsai, Ching-Hsun Huang, Han-Yi Hsieh, Jing-Jia Huang, Ching-Cheng Wang
  • Patent number: 11280021
    Abstract: A method of controlling chemical concentration in electrolyte includes measuring a chemical concentration in an electrolyte, wherein the electrolyte is contained in a tank; and increasing a vapor flux through an exhaust pipe connected to the tank when the measured chemical concentration is lower than a control lower limit value.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chang Huang, You-Fu Chen, Yu-Chi Tsai, Chu-Ting Chang
  • Patent number: 11280473
    Abstract: An optical lens, a light-emitting device and a backlight module are provided. The optical lens is used for adjusting light emitted from a light-emitting unit. The optical lens includes a light-incident surface and a light-emitting surface. The light-incident surface encloses a space for accommodating the light-emitting unit. The light-emitting surface is used for receiving and emitting light entering the optical lens via the light-incident surface. The optical lens has an optical axis, with respect to which the light-incident surface is asymmetric.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: March 22, 2022
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chih-Wei Chien, Li-Wei Tseng, Shau-Yu Tsai
  • Patent number: 11282767
    Abstract: A semiconductor package structure includes a package substrate and a semiconductor die. The package substrate includes a plurality of hollow vias extending through the package substrate. The semiconductor die is electrically connected to the package substrate. The hollow vias are disposed under the semiconductor die.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: March 22, 2022
    Assignee: ADVANCED SEMICONDUTOR ENGINEERING, INC.
    Inventors: Hsin-En Chen, Ian Hu, Jung-Che Tsai
  • Patent number: 11283412
    Abstract: A low noise amplifier circuit includes an input stage circuit, a first output stage circuit, and a second output stage circuit. The input stage circuit is configured to receive an input signal and to generate a bias signal. The first output stage circuit corresponding to a first wireless communication and is configured to be biased according to the bias signal and a first control signal, in order to generate a first output signal, in which the first control signal is for setting a first gain of the first output stage circuit. The second output stage circuit corresponding to a second wireless communication and is configured to be biased according to the bias signal and a second control signal, in order to generate a second output signal, in which the second control signal is for setting a second gain of the second output stage circuit.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: March 22, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chia-Jun Chang, Chia-Yi Lee, Ping-Hsuan Tsai, Ka-Un Chan
  • Patent number: 11282810
    Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo