Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate, and selectively forming a gate material over the gate dielectric layer. A gate dielectric protection layer is formed over the gate dielectric layer, and a first sidewall spacer is formed over the gate dielectric protection layer and flanking a side of the gate material. The gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to outside of the first sidewall spacer.

Abstract: The present disclosure relates to an integrated circuit having an interconnect wire contacting an upper electrode of the RRAM (resistive random access memory) device, and a method of formation. In some embodiments, the integrated circuit comprises an RRAM device having a dielectric data storage layer disposed between a lower electrode and an upper electrode. An interconnect wire contacts an upper surface of the upper electrode, and an interconnect via is arranged onto the interconnect wire. The interconnect via is set back from one or more outermost sidewalls of the interconnect wire. The interconnect wire has a relatively large size that provides for a good electrical connection between the interconnect wire and the upper electrode, thereby increasing a process window of the RRAM device.

Abstract: The invention is to provide a method and kit based on recombinase polymerase amplification (RPA) and lateral flow dipstick (LFD) for detection of caprine arthritis-encephalitis virus (CAEV) infection. The method and kit are suitable for both laboratory and field application, and are specific and sensitive for detecting CAEV proviral DNA in goats in a fast manner. The method and lit of the invention are also applicable for on-site utilization at farms and should be useful in both eradication programs and epidemiological studies.

Abstract: A semiconductor structure includes an oval-shaped pad and a dielectric layer. The oval-shaped pad is on a substrate and includes a major axis corresponding to the largest distance of the oval-shaped pad. The major axis is toward a geometric center of the substrate. The dielectric layer covers the substrate and surrounds the oval-shaped pad.

Abstract: An LED lighting module comprises a plurality of serially-connected LED strings, which include N LED strings from a first LED string to an Nth LED string, and each LED string has a specific driven voltage. The control method comprises steps of: (a) receiving an AC voltage signal and converting the AC input signal into a first AC signal; (b) receiving the first AC signal and converting the first AC signal into a first DC signal; and (c) if the first DC signal exceeds the sum of the driven voltages from the first LED string to an nth LED string, driving the serially-connected LED strings from the first LED string to the nth LED string sequentially, wherein n is smaller than or equal to N, so as to adjust the correlated color temperature of the light emitted by the LED lighting module.

Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.

Abstract: The present disclosure relates to a method of manufacturing a memory device. The method is performed by forming an inter-layer dielectric (ILD) layer over a substrate, and forming an opening within a dielectric protection layer over the ILD layer. A bottom electrode layer is formed within the opening and over the dielectric protection layer. A chemical mechanical planarization (CMP) process is performed on the bottom electrode layer to form a bottom electrode structure having a planar upper surface and a projection that protrudes outward from a lower surface of the bottom electrode structure to within the opening. A memory element is formed over the bottom electrode structure, and a top electrode is formed over the memory element.

Abstract: Systems and methods are provided for receiver nonlinearity estimation and cancellation. During processing of received radio frequency (RF) signals, it may be determined when one or more other signals, different from the received RF signals, cause nonlinearity affecting processing of the RF signals, and one or more cancellation adjustments may be applied during processing of the RF signals, for mitigating effects of the nonlinearity. Determining the one or more cancellation adjustments may be based on narrowband (NB) estimation of the effects of the nonlinearity, and the one or more cancellation adjustments may be configured as wideband (WB) corrections. The NB estimation may be applied based on channelization of the received RF signals. The NB estimation may comprise generating reference nonlinearity information relating to the one or more other signals, and generating, based on the reference nonlinearity information, control data for configuring the one or more cancellation adjustments.

Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.

Abstract: A method for forming a deep trench structure is provided. The method includes forming a first recess in a top portion of a substrate and forming a first protective layer on sidewalls of the first recess. The method includes etching a middle portion of the substrate by using the first protective layer as a mask to form a second recess and forming a second protective layer on sidewalls of the second recess. The method also includes etching a bottom portion of the substrate by using the second protective layer as a mask to form a third recess; and removing the first protective layer and the second protective layer to form a deep trench structure. The deep trench structure is constructed by the first recess, the second recess and the third recess, and the deep trench structure has a stair shape.

Abstract: Among other things, techniques and systems are provided for identifying when a pixel of an image sensor is in an idle period. A flag is utilized to differentiate when the pixel is in an idle period and when the pixel is in an integration period. When the flag indicates that the pixel is in an idle period, a blooming operation is performed on the pixel to reduce an amount of electrical charge that has accumulated at the pixel or to mitigate electrical charge from accumulating at the pixel. In this way, the blooming operation reduces a probability that the photosensitive sensor becomes saturated during an idle period of the pixel, and thus reduces the likelihood of electrical charge from a pixel that is not intended contribute to an image from spilling over and potentially contaminating a pixel that is intended to contribute to the image.

Abstract: A method of forming a semiconductor image sensing device includes: providing a semiconductor substrate; forming a radiation sensitive region and a peripheral region in the semiconductor substrate, wherein the peripheral region surrounds the radiation sensitive region and includes a top surface projected from a backside of the semiconductor substrate and a sidewall coplanar with a sidewall of the semiconductor substrate and perpendicular to the top surface; forming a photon blocking spacer in the peripheral region, wherein the photon blocking spacer covers a portion of the sidewall of the peripheral region; and forming an anti reflective coating adjacent to the photon blocking layer.

Abstract: A semiconductor device includes a carrier wafer, a device layer, a first semiconductor layer and a second semiconductor layer. The device layer is disposed on the carrier wafer. The first semiconductor layer is disposed on the device layer, and has a first side face and a second side face opposite to the first side face, in which the first side face is adjacent to the device layer. The second semiconductor layer is disposed on the first semiconductor layer, and has a third side face and a fourth side face opposite to the third side face, in which the fourth side face of the second semiconductor layer is adjacent to the second side face of the first semiconductor layer, and the second semiconductor layer is implanted and annealed.

Abstract: A camera having a gyro and accelerometer stabilizes a video recording by the following steps. First, gyro data and acceleration data are synchronized with a frame of video data. The gyro data and the acceleration data are fused together to get a space domain rotation matrix that corresponds to the frame. The frame is adjusted based on the space domain rotation matrix. Next, at least one feature of the adjusted frame is detected. A modified rotation matrix is determined by comparing the at least one detected feature of the adjusted frame with a corresponding feature in a neighboring frame of the video data. Finally, the adjusted frame is further adjusted based on the modified rotation matrix.

Abstract: An adjustment structure of bridle including a bridle, rotating shaft, and a knob is provided. The bridle has a rack. The rotating shaft has a first ring gear and a second ring gear both around an axis, wherein the first ring gear is coupled to the rack, such that the rotating shaft moves along the bridle by rotating about the axis itself The knob is rotated about the axis and moved along the axis to be movably coupled to the rotating shaft. The knob has a third ring gear to be engaged with or released from the second ring gear by the knob moving along the axis. When the third ring gear is engaged with the second ring gear, the knob is forced to drive the rotating shaft to rotate about the axis.

Abstract: The present invention discloses a connecting rod-type lower limb exoskeleton rehabilitation robot, comprising a treadmill, two pneumatic muscle frames, two transmission devices and two lower limb exoskeletons; the pneumatic muscle frame includes a thigh rotating shaft, a calf rotating shaft, a hip joint shaft, pneumatic muscles and a support frame; the transmission device includes a thigh transmission mechanism and a calf transmission mechanism; the thigh transmission mechanism is a parallel four-connecting-rod mechanism composed of a thigh rotating arm, a thigh connecting rod and a thigh skeleton; the calf transmission mechanism includes two four-connecting-rod mechanisms; and the lower limb exoskeleton is connected to the pneumatic muscle frame through the transmission device.

Abstract: A fuse array and a memory device are provided in the invention. The fuse array includes a plurality of fuses and a plurality of first D flip-flops. The fuses are configured to generate a plurality of data signals. Each of the first D flip-flops is respectively coupled to one corresponding fuse of the fuses to receive the data signal from the corresponding fuse and the first D flip-flops transmit a clock signal and the data signal to a plurality of second D flip-flops comprised in a plurality of memory cells. The first D flip-flops are connected in series and the second D flip-flops are connected in series.

Abstract: A design method for creep-fatigue strength of a plate-fin heat exchanger. The method includes preliminarily designing the plate-fin heat exchanger according to its service requirements, making a primary stress assessment for the plate-fin heat exchanger, calculating the equivalent mechanical and thermophysical parameters of the plate-fin heat exchanger core to satisfy the allowable stress requirement, performing a thermal fatigue analysis for the plate-fin heat exchanger based on these parameters and then calculating the fatigue life and creep life of the plate-fin heat exchanger to accomplish the comprehensive design of the plate-fin heat exchanger in the high-temperature service. The design method provides an effective method for the high temperature design of the plate-fin heat exchanger.

Abstract: A method and device for sound effect processing, and a non-transitory storage medium. The method includes the following actions. A task manager is traversed to determine whether a sound effect service process for a sound effect service exists. Responsive to determining that the sound effect service process exists, whether the sound effect service process is a system process of a system, is determined. When the sound effect service process is not a system process of the system, the sound effect service process is set to be a system process of the system.

Abstract: A semiconductor device includes a first electronic component, a second electronic component and a plurality of interconnection structures. The first electronic component has a first surface. The second electronic component is over the first electronic component, and the second electronic component has a second surface facing the first surface of the first electronic component. The interconnection structures are between and electrically connected to the first electronic component and the second electronic component, wherein each of the interconnection structures has a length along a first direction substantially parallel to the first surface and the second surface, a width along a second direction substantially parallel to the first surface and the second surface and substantially perpendicular to the first direction, and the length is larger than the width of at least one of the interconnection structures.