Abstract: The present invention provides a method of laminating a film for a dye-sensitized cell. First, a composite film is taken by a robotic arm, in which the composite film includes a release layer, a protective layer and a hot glue layer between the release layer and the protective layer, and the release layer is removed by the robotic arm. Then, the hot glue layer is precisely attached to a substrate by a target positioning step. Next, the protective layer is removed by the robotic arm.

Abstract: A gate-controlled bipolar junction transistor includes a substrate, an emitter region, a base region disposed on one side of the emitter region, and a collector region disposed on one side of the base region and being opposite to the emitter region. The emitter region includes first fin structures, first metal gates extending across the first fin structures, and an emitter contact plug on the first fin structures. A gate contact region is disposed between the emitter region and the base region. Each of the first metal gates includes an extended contact end portion protruding toward the base region. The extended contact end portion is disposed within the gate contact region. A gate contact is disposed on the extended contact end portion.

Abstract: A structure includes first, second, third, and fourth conductive segments, and a gate. The first and second conductive segments are in a first conductive layer and configured as first and second terminals of a first transistor of a first type. The third and fourth conductive segments are in a second conductive layer stacked over the first conductive layer and configured as first and second terminals of a second transistor of a second type. The first gate is arranged, in a first direction, between the first and third conductive segments and the second and fourth conductive segments. The gate is configured as a control terminal of the first transistor and a control terminal of the second transistor, the first conductive segment is offset from the third conductive segment along the first direction, and the second conductive segment is offset from the fourth conductive segment along the first direction.

Abstract: An image processing method includes: inputting a to-be-processed image into a neural network; and forming discrete feature data of the to-be-processed image via the neural network, where the neural network is trained based on guidance information, and during the training process, the neural network is taken as a student neural network; the guidance information includes: a difference between discrete feature data formed by a teacher neural network for an image sample and discrete feature data formed by the student neural network for the image sample.

Abstract: The present disclosure provides a benzo diheterocyclic compound having a structure represented by Formula (I). In Formula (I), Y1 and Y2 are oxygen or sulfur; Ar1 and Ar2 are each independently selected from a group consisting of single bond, a substituted or unsubstituted phenyl, a substituted or unsubstituted naphthyl, a substituted or unsubstituted anthracyl, a substituted or unsubstituted phenanthryl, a substituted or unsubstituted acenaphthylenyl, and a substituted or unsubstituted aromatic heterocyclic group; m and n are integers independently selected from 0 and 1; D1 and D2 are aryl or heteroaryl, Ar3 and Ar4 are aryl or heteroaryl, and R1 is hydrogen, phenyl, or naphthyl. When the benzo diheterocyclic compound is used as a capping layer of a cathode, it will not interfere light emission of an OLED, and the OLED can maintain a high color purity.

Abstract: A manufacturing method is provided. The manufacturing method includes the following steps. Firstly, a substrate and a light-emitting component are provided, wherein the light-emitting component is disposed on the substrate. Then, a wavelength conversion layer is provided, wherein the wavelength conversion layer includes a high-density phosphor layer and a low-density phosphor layer. Then, the high-density phosphor layer is adhered to the light-emitting component by an adhesive. Then, a reflective layer is formed above the substrate, wherein the reflective layer covers a lateral surface of the light-emitting component, a lateral surface of the adhesive and a lateral surface of the wavelength conversion layer.

Abstract: An antenna includes a first portion and a second portion. The first portion is of a first shape and the second portion is of a second shape. The second portion is connected to the first portion by a junction. The antenna operates in a first frequency band and a second frequency band.

Abstract: A semiconductor device includes a semiconductor substrate, a radiation-sensing region, at least one isolation structure, and a doped passivation layer. The radiation-sensing region is present in the semiconductor substrate. The isolation structure is present in the semiconductor substrate and adjacent to the radiation-sensing region. The doped passivation layer at least partially surrounds the isolation structure in a substantially conformal manner.

Abstract: New radio (NR) unlicensed (NR-U) multi-channel access is disclosed for low-radio frequency (RF)-capable user equipment (UE). A base station may enable multi-channel access when single operator operations cannot be guaranteed within a shared communication spectrum. The primary and secondary channels are defined within the shared communication channel. The base station may then transmit a configuration message to one or more low-RF UEs that identifies the charnels and directs the UEs to monitor the primary channel for a successful listen before talk (LBT) indicator. The base station performs an LBT procedure on the primary channel and the secondary channel and signals the low-RF UEs to re-tune to the secondary channel for communication during a current transmission opportunity.

Abstract: A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_2nd level (first M_2nd pattern) or a first conductive pattern in the M_1st level (first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and changing a size of the candidate pattern thereby revising the layout diagram.

Abstract: A detection device includes a light refraction structure and a resistance detection circuit. The light refraction structure includes a substrate, a conductive layer, and a refraction layer. The conductive layer and the refraction layer are formed on the substrate. The conductive layer includes a resistance. The resistance detection circuit is electrically coupled to the conductive layer and is adapted to detect the resistance of the conductive layer. The resistance detection circuit generates a detection signal according to a change in the resistance, and the detection signal represents a state of the refraction layer.

Abstract: The present invention provides QMAX based devices, kits, and methods for rapid, easy to use, and/or inexpensive detection of assaying.

Abstract: A printing method includes outputting multiple delay signals corresponding to multiple pixels by a delay latch array. The delay signals are calculated according to the largest and each resistance value corresponding to the multiple pixels in a thermal printing head respectively; and controlling the pixels to print according to the delay signals by the multiple pixel switches.

Abstract: A method and associated computer program for predicting an electrical characteristic of a substrate subject to a process. The method includes determining a sensitivity of the electrical characteristic to a process characteristic, based on analysis of electrical metrology data including electrical characteristic measurements from previously processed substrates and of process metrology data including measurements of at least one parameter related to the process characteristic measured from the previously processed substrates; obtaining process metrology data related to the substrate describing the at least one parameter; and predicting the electrical characteristic of the substrate based on the sensitivity and the process metrology data.

Abstract: The blinking control method comprises the following steps. First, detect a current blinking signal, wherein the current blinking signal occurs at a current blinking time point. Afterwards, obtain a predicted spontaneous blinking time slot according to the current blinking time point, a minimum spontaneous blinking calibration time interval, and a maximum spontaneous blinking calibration time interval. Afterwards, detect a next blinking signal. Afterwards, determine if the next blinking signal occurs within the predicted spontaneous blinking time slot. Determine if the next blinking signal belongs to a spontaneous blinking when the next blinking signal occurs within the predicted spontaneous blinking time slot. Determine if the next blinking signal belongs to a controlled blinking when the next blinking signal occurs outside the predicted spontaneous blinking time slot.

Abstract: A calibration method for calibrating the position error in the point of interest induced from the stage of the defect inspection tool is achieved by controlling the deflectors directly. The position error in the point of interest is obtained from the design layout database.

Abstract: A method of integrated circuit (IC) fabrication includes exposing a plurality of channel regions including a p-type channel region and an n-type channel region; forming a gate dielectric layer over the exposed channel regions; and forming a work function metal (WFM) structure over the gate dielectric layer. The WFM structure includes a p-type WFM portion formed over the p-type channel region and an n-type WFM portion formed over the n-type channel region, and the p-type WFM portion is thinner than the n-type WFM portion. The method further includes forming a fill metal layer over the WFM structure such that the fill metal layer is in direct contact with both the p-type and n-type WFM portions.

Abstract: A device may wirelessly communicate according to a first radio access technology (RAT) within a first bandwidth part (BWP) of a frequency spectrum in which wireless communications according to other RAT(s) also take place. The device may be instructed to operate/communicate within a second BWP of the frequency spectrum responsive to the device successfully completing a listen-before-talk (LBT) procedure within a specified portion of the second BWP, where the second BWP contains the first BWP while the first BWP does not contain the specified portion of the second BWP. The device may also be instructed to operate/communicate within a specified frequency band (SFB) of the frequency spectrum responsive to the device successfully completing an LBT procedure within the SFB, where the SFB is not contiguous with the frequency band that includes the first BWP. The device may then simultaneously operate within the second frequency band and the first frequency band.

Abstract: A transport system is provided. The transport system includes a stocker configured to store an assigned wafer carrier and having a gate port. The transport system also includes a semiconductor apparatus configured to transmit a request signal including a processed time according to a processing wafer carrier loaded on the semiconductor apparatus. The transport system further includes a vehicle configured to transport the assigned wafer carrier from the gate port to the semiconductor apparatus and a control system configured to control the vehicle. When the control system receives the request signal, the control system controls the stocker to transport the assigned wafer carrier inside of the stocker to the gate port at a start time, which is earlier than the processed time, and the control system controls the vehicle to transport the assigned wafer carrier from the gate port to the semiconductor apparatus.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.