Abstract: A testing system includes a subtractor and a divider. The subtractor is configured to receive a first voltage of a circuit being tested and a second voltage of the circuit, and to derive a difference between the first voltage and the second voltage. The divider is configured to receive the difference between the first voltage and the second voltage, and to derive a resistance of the circuit by dividing (i) the difference between the first voltage and the second voltage by (ii) a difference between a first current applied to the circuit and a second current applied to the circuit. The first voltage is corresponding to the first current, and the second voltage is corresponding to the second current.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first stacked structure, a second stacked structure, an isolation layer and a gate. The first stacked structure is disposed on a substrate, and includes a first GaN channel layer disposed on the substrate and having an N crystal phase and a first barrier layer disposed on the first GaN channel layer. The second stacked structure is disposed on the substrate, and includes a second GaN channel layer disposed on the substrate and having a Ga crystal phase and a second barrier layer disposed on the second GaN channel layer. The isolation layer is disposed between the first stacked structure and the second stacked structure. The gate is disposed on the first stacked structure, the isolation layer and the second stacked structure.

Abstract: A data inconsistency is detected in a file system data block of a file system. The file system includes a set of files, each file includes a set of file system data blocks. Information regarding a file including the data inconsistency is provided to a client of the file system. Based on the information, the client is enabled to determine an action for recovering from the data inconsistency.

Abstract: A multi-core processor supporting cache consistency, a method and apparatus for data writing, and a method and apparatus for memory allocation, as well as a system by use thereof. The multi-core processor supporting cache consistency includes a plurality of cores, the plurality of cores corresponding to respective local caches. A local cache of a core of the plurality of cores is responsible for caching data in a different range of addresses in a memory space and a core of the plurality of cores accesses data in a local cache of another core of the plurality of core via an interconnect bus.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.

Abstract: A plasmonic sensor includes at least a substrate and a thin film metallic glass formed on the substrate. The dielectric constant (?r) of the thin film metallic glass is negative. Since the thin film metallic glass with negative ?r is used in the plasmonic sensor, the material cost can be significantly reduced, the mechanical property can be improved, and the optoelectronic property can be increased. Since the thin film metallic glass is a kind of supercooled alloy with amorphous structure, it can be applied for imprinting deformation and amorphous without grain boundary scattering.

Abstract: A method for making a polymer with a porous layer from a solid piece of polymer is disclosed. In various embodiments, the method includes heating a surface of a solid piece of polymer to a processing temperature and holding the processing temperature while displacing a porogen layer through the surface of the polymer to create a matrix layer of the solid polymer body comprising the polymer and the porogen layer. In at least one embodiment, the method also includes removing at least a portion of the layer of porogen from the matrix layer to create a porous layer of the solid piece of polymer.

Abstract: An encryption and decryption method in a virtualization system, where the virtualization system includes a virtual machine monitor (VMM) and an encryption and decryption virtual machine. The VMM includes a control module, the encryption and decryption virtual machine records a first association relationship between a hard disk image identifier and a key, the key includes an encryption key, and the virtualization system records a second association relationship between the hard disk image identifier and a hard disk image attribute. The control module in the VMM is configured to determine whether to-be-written data needs to be encrypted and forward the to-be-written data, which reduces system complexity of the VMM. In addition, encryption or decryption is processed without occupying a resource in the VMM.

Abstract: A power consumption estimation method is applied to an image with N rows of pixels, and comprises a pixel estimation procedure comprising performing an estimation sub-procedure pixel by pixel for each of a plurality of pixels in one row of the N rows of pixels to obtain a plurality of pixel energy consumption values respectively corresponding to the plurality of pixels in said one row of the N rows, and obtaining a row power consumption value corresponding to said one row of the N rows according to the plurality of pixel energy consumption values. The estimation sub-procedure comprises obtaining pixel content information corresponding to one of the plurality of pixels, and determining the pixel energy consumption value according to the pixel content information. The pixel energy consumption value indicates pixel energy consumption generated by performing a predetermined image processing procedure for said one of the plurality of pixels.

Abstract: Mobile originated and terminated data transmissions are discussed. Communication devices such as user equipment (UE) can be dynamically configured by a network to send and receive data. When a UE connects to a new network, the network can determine mobility of the UE and/or the network resource allocation granularity. Based at least on the network's determinations, the UE can be configured such that access data having a comparatively long life span is used and reused for multiple data transmissions. In some scenarios, access data can be refreshed after expiration of a period of time. Refresh time can be equal to expected life span of reusable access data. After UE configuration, the UE performs mobile originated and terminated data transmissions according to the configuration. Other aspects, embodiments, and features are also claimed and described.

Abstract: An aspect of the disclosure provides a processing method for display data applied in a computing device, which processing method includes: determining a region of interest in the display area of the computing device; compressing data of an image in the display area; and transmitting data of an image of the region of interest and the compressed image data in the display area. The disclosure further provides a corresponding processing device and display device.

Abstract: A method of making a semiconductor device that includes forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region having side portions and a bottom portion that exposes the substrate. The method also includes forming a dielectric barrier layer in the contact region to cover the side portions and forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region. The method can include forming a conductive layer over the conductive blocking layer and forming a conductive barrier layer over the conductive layer. The method can further include forming a silicide region in the substrate beneath the conductive layer.

Abstract: A magnetic resonance angiography method includes: in a plurality of first repeated collecting periods, a first echo signal set is formed by flow-compensated first echo signals and a second echo signal set is formed by flow-compensated second echo signals; in a plurality of second repeated collecting periods, a third echo signal set is formed by flow-compensated third echo signals and a fourth echo signal set is formed by flow-dephased fourth echo signals; a venous blood vessel image is reconstructed according to the second echo signal set; an arteriovenous blood vessel image is obtained according to the first echo signal set, the third echo signal set and the fourth echo signal set; and an arterial blood vessel image is obtained according to the venous blood vessel image and the arteriovenous blood vessel image.

Abstract: A paravalvular leak resistant prosthetic heart valve system including a stent frame, a valve structure and a sealing mechanism. The stent frame has a surface. The valve structure is associated with the stent frame. The sealing mechanism at least partially extends over the surface of the stent frame. The sealing mechanism includes at least one semi-permeable membrane and an osmotic gradient driving material.

Abstract: A digital control system for voltage regulation and a method thereof are disclosed. The digital control system includes an adjustable voltage regulation circuit having multiple discrete conversion ratios, an error generator, a digital controller and a conversion ratio controller. The adjustable voltage regulation circuit, the error generator, the digital controller and the conversion ratio controller form a closed loop control system. The adjustable voltage regulation circuit includes a conversion ratio controlling terminal receiving a conversion ratio signal. The error generator compares an output voltage of the adjustable voltage regulation circuit with a reference voltage to generate an error voltage, and the digital controller outputs a digital control signal to the conversion ratio controller according to the error voltage.

Abstract: The present application discloses a quick recovery method, device and system of a virtual machine.

Abstract: A method and a device for automatically reversing a vehicle are provided. A forward track of a target vehicle is recorded in a forward process of the target vehicle. The target vehicle is controlled to be reversed from a current position and the target vehicle is controlled to be reversed along the forward track by adjusting a steering wheel angle of the target vehicle at each reversing moment, when an automatic reversing instruction for the target vehicle is detected after the target vehicle stops moving forward. The target vehicle is controlled to stop being reversed when a reversing stop instruction for the target vehicle is detected in a reversing process.

Abstract: The present disclosure discloses a space separator for a sorting robot. A preferred embodiment of the space separator may comprise: at least one layer of trays, an axial center of the tray being provided with a shaft, the tray being provided with a slot in which an openable tray door is provided, an end of the tray extending upwards to form a tray wall; wherein the space separator is disposed along the shaft of the tray till the tray wall, the space separator being rotatable about the shaft of the tray. This embodiment enables a flexible adjustment of the number and size of the storage bins divided on the tray with the space separator.

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

Abstract: A memory access technology applied to a computer system includes a first-level memory, a second-level memory, and a memory controller. The first-level memory is configured to cache data in the second-level memory. A plurality of access requests for accessing different memory blocks has a mapping relationship with a first cache line in the first-level memory, and the memory controller compares tags of the plurality of access requests with a tag of the first cache line in a centralized manner to determine whether the plurality of access requests hit the first-level memory.