Patents by Inventor An Wu

An Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11914941
    Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Rachid Salik, Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang
  • Patent number: 11910837
    Abstract: A vaporizer apparatus is provided. The vaporizer apparatus includes a cartridge body and a child resistant device. The cartridge body includes an activation button and an inhalation portion. The inhalation portion is operable to allow a user to draw vapor from the cartridge body. The child resistant device includes an outer cap and an inner cap nestled within an inside chamber of the outer cap. The inner cap is coupled with the cartridge body to prevent access to the inhalation of the cartridge body. In a locked configuration, the outer cap and the inner cap are disengaged such that the outer cap is freely movable independent of the inner cap. In an unlocking configuration, the outer cap and the inner cap are engaged with one another such that movement of the outer cap detaches the child resistant device from the cartridge body.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: February 27, 2024
    Assignee: Clear IP Corporation
    Inventor: Jeff Wu
  • Patent number: 11917851
    Abstract: Provided is a packaging structure for packaging a display device, the packaging structure comprising: at least one composite film layer, wherein the composite film layer comprises an inorganic pattern and an organic pattern, the inorganic pattern comprises a plurality of curved structures arranged at intervals, the organic pattern comprises a first organic sub-pattern, and the first organic sub-pattern and the inorganic pattern are located in a same layer and are complementary in position; and wherein an orthographic projection of the composite film layer onto the display device at least covers a display area of the display device. A display substrate, a display apparatus, and a method for packaging a display device are also provided.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: February 27, 2024
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Youyuan Hu, Mengyu Luan, Xinfeng Wu, Bowen Liu, Xinzhu Wang, Fei Li, Huihui Li
  • Patent number: 11916102
    Abstract: A method for forming a double-sided capacitor structure includes: providing a base, the base including a substrate, a plurality of capacitor contacts located in the substrate, a stack structure located on a surface of the substrate and a plurality of capacitor holes running through the stack structure and exposing the capacitor contacts, the stack structure including sacrificial layers and support layers which are stacked alternately; successively forming a first electrode layer, a first dielectric layer and a second electrode layer on inner walls of the capacitor holes; forming a first conductive filling layer in the capacitor holes; forming an auxiliary layer for sealing the capacitor holes; removing a part of the auxiliary layers and several of the support layers and the sacrificial layers to expose the first electrode layer; and, forming a second dielectric layer and a third electrode layer.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: February 27, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Wenjia Hu, Han Wu, Yong Lu
  • Patent number: 11913324
    Abstract: An apparatus for downhole multi-dimensional imaging includes an acquisition unit configured to acquire a formation resistivity signal, an ultrasonic echo signal and an orientation signal regularly; a sector calculation unit configured to calculate, based on said orientation signal, a sector where a currently acquired signal is from; and a multi-dimensional imaging unit, configured to calculate, based on the signals acquired by the acquisition unit, data of resistivity, distance from a drilling tool to a borehole wall and ultrasonic echo amplitude, and distribute said data into all sectors for feature recognition and extraction, thus obtaining key features characterizing a current formation being drilled, said key features being transmitted to ground for guiding drilling process. The structural complexity and the length of the downhole imaging measurement instrument can be reduced, and feature recognition can be directly performed on the imaging data underground.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: February 27, 2024
    Assignees: CHINA PETROLEUM & CHEMICAL CORPORATION, SINOPEC RESEARCH INSTITUTE OF PETROLEUM ENGINEERING
    Inventors: Yijin Zeng, Wei Zhang, Weining Ni, Xin Li, Lipeng Yan, Jinping Wu, Yuefa Hu, Lishuang Wang, Zuyang Zhu, Jintai Mi
  • Patent number: 11912520
    Abstract: This application discloses a rewinding apparatus and a rewinding method. The rewinding apparatus is configured to rewind a strip. The rewinding apparatus includes a rewinding mechanism and a switching mechanism. The rewinding mechanism includes two shafts that are opposite to each other along a first direction and spaced out. The two shafts are configured to rewind the strip along different conveyance paths separately. The switching mechanism includes a moving roller. The moving roller is configured to drive the strip to switch from one shaft to another shaft so that the strip switches from one conveyance path to another conveyance path. The rewinding apparatus and rewinding method disclosed in this application achieve high space efficiency and high switching efficiency.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: February 27, 2024
    Assignee: Contemporary Amperex Technology Co., Limited
    Inventors: Ruchu Yu, Shaojun Qiu, Tiefeng Wu
  • Patent number: 11913939
    Abstract: Methods and systems for performing assays in compartmentalized nano-volumes to screen for functional bispecific or multispecific biologics, including: providing a plurality of at least two distinct types of cells, wherein two or more first-type cells are engineered to express substantially a single genetic-variant per cell for a bispecific or multispecific biologic in a secreted form, wherein two or more second-type cells are selected or engineered to produce a positive reporter molecule signal that is triggered by a functional variant of the said biologic expressed by a first-type cell; providing a plurality of compartmentalized nano-volumes, wherein two or more nano-volumes are each provided with substantially one first-type cell, and one or more second-type cell(s); incubating the said nano-volumes over a period of time to allow the expression and secretion of the said biologics inside the said nano-volumes; collecting data representing the positive reporter molecule signal triggered by secreted biologics
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: February 27, 2024
    Assignee: Amberstone Biosciences, Inc.
    Inventors: George Guikai Wu, Yonglei Shang
  • Patent number: 11916298
    Abstract: A patch antenna comprises a multilayer printed circuit board that includes a calibration network, an array of patch radiators and a feed network. In some embodiments, the multilayer printed circuit board includes a plurality of dielectric substrates, wherein the array of patch radiators is provided on a dielectric substrate different from the dielectric substrate on which the calibration network is provided, and the dielectric substrate provided with the array of patch radiators is provided above the dielectric substrate provided with the calibration network.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: February 27, 2024
    Assignee: CommScope Technologies LLC
    Inventors: Xun Zhang, Bo Wu, Hangsheng Wen, Zhigang Wang, Jian Zhang, Ligang Wu
  • Patent number: 11915733
    Abstract: A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Jui-Jen Wu, Jen-Chieh Liu, Meng-Fan Chang
  • Patent number: 11916684
    Abstract: Aspects of the present disclosure provide apparatus, methods, processing systems, and computer readable mediums for channel and/or resource selection for sidelink communications. In some cases, a transmitter user equipment UE may transmit, on a sidelink channel used for communicating with other UEs, a control message indicating at least one range, monitor for feedback associated with detection of the control message by one or more other UEs within the indicated range, and transmit data if the feedback indicates at least that the sidelink channel is free.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: February 27, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Shuanshuan Wu, Kapil Gulati, Arthur Gubeskys
  • Patent number: 11915311
    Abstract: A method, apparatus, and server for generating a user score based on social networking information is provided. In the disclosed method, by processing circuitry of an information processing apparatus, default annotation information of a plurality of sampled users, an ith user score and an ith relative user score for each of the sampled users are obtained. A user score model is trained according to the ith user score of the respective sampled user, the ith relative user score of the respective sampled user, and the default annotation information of the respective sampled user. An (i+1)th user score of the respective sampled user is subsequently calculated and a trained user score model, for each of the sampled users, is obtained when the (i+1)th user score for the respective sampled user satisfies a training termination condition, The method provides a solution to evaluate the user score for a use when personal information of the user is missing or incorrect.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: February 27, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Peixuan Chen, Qian Chen, Lin Li, Sanping Wu, Weiliang Zhuang
  • Patent number: 11915958
    Abstract: An apparatus and an operating method for automated wafer carrier handling are provided. The operation method includes bring a base frame and an engaging mechanism of an automated wafer carrier handling apparatus into abutting contact with a top flange mounted on a wafer carrier to limit at least one degree of freedom of movement of the top flange, where the engaging mechanism is disposed on the base frame; transporting the wafer carrier to a destination location by the automated wafer carrier handling apparatus; and releasing the top flange mounted on the wafer carrier from the automated wafer carrier handling apparatus at the destination location.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ren-Hau Wu, Cheng-Lung Wu, Jiun-Rong Pai, Cheng-Kang Hu
  • Patent number: 11915957
    Abstract: A multiple die container load port may include a housing with an opening, and an elevator to accommodate a plurality of different sized die containers. The multiple die container load port may include a stage supported by the housing and moveable within the opening of the housing by the elevator. The stage may include one or more positioning mechanisms to facilitate positioning of the plurality of different sized die containers on the stage, and may include different portions movable by the elevator to accommodate the plurality of different sized die containers. The multiple die container load port may include a position sensor to identify one of the plurality of different sized die containers positioned on the stage.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Huang, Cheng-Lung Wu, Yi-Fam Shiu, Yu-Chen Chen, Yang-Ann Chu, Jiun-Rong Pai
  • Patent number: 11916067
    Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
  • Patent number: 11916633
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit, to another UE, a sidelink channel state information reference signal (S-CSI-RS) and an indication associated with triggering a non-codebook based precoded S-CSI-RS. The UE may receive, from the other UE, the non-codebook based precoded S-CSI-RS. The UE may transmit, to the other UE, a non-codebook based channel state information (CSI) report medium access control (MAC) control element (MAC-CE) that includes an indication of one or more selected precoding beams based at least in part on the non-codebook based precoded S-CSI-RS. Numerous other aspects are described.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: February 27, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Yisheng Xue, Chih-Hao Liu, Jing Sun, Xiaoxia Zhang, Shuanshuan Wu
  • Patent number: 11916817
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment may generate a pseudorandom noise (PN) sequence, modulate the PN sequence based at least in part on a modulation order parameter, and transmit the PN sequence in one or more symbols prior to transmitting sidelink data. The one or more symbols used to transmit the PN sequence may be used for automatic gain control (AGC) training at a receiving device. The user equipment may then transmit the sidelink data in a plurality of symbols that are subsequent in time relative to the one or more symbols used to transmit the PN sequence, and the receiving device may process the sidelink data based on the AGC training. Numerous other aspects are provided.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: February 27, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Shuanshuan Wu, Kapil Gulati, Sudhir Kumar Baghel, Arthur Gubeskys, Arjun Bharadwaj, Tien Viet Nguyen
  • Patent number: 11914693
    Abstract: A fingerprint recognition method includes, when a fingerprint authentication module is in a disabled state, receiving a touch operation used to trigger an application program. If fingerprint authentication is not required for execution of the application program, the fingerprint recognition module is kept in a disabled state, and after the application program has been executed for specific duration, the fingerprint authentication module is enabled again, to perform the fingerprint authentication.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: February 27, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jiejing Huang, Huangwei Wu
  • Patent number: 11917401
    Abstract: Methods, apparatuses, and computer-readable medium for directional security are provided. An example method may include receiving, from a wireless device, a configuration for a set of shared keys. The example method may further include receiving, from a second UE, at least one message or signal including a location of the second UE, the received at least one message or signal being associated with an angle of arrival. The example method may further include configuring a key from the set of shared keys based on at least one of the received configuration, the location of the second UE, the AoA of the received at least one message or signal, or a location of the first UE. The example method may further include generating one or more ranging signals based on the configured key, the one or more ranging signals being directionally secure based on the location of the second UE.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: February 27, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Anantharaman Balasubramanian, Shuanshuan Wu, Kapil Gulati, Navid Abedini, Junyi Li, Sourjya Dutta, Preeti Kumari
  • Patent number: D1015680
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: February 27, 2024
    Inventor: Junhua Wu
  • Patent number: D1016296
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 27, 2024
    Assignee: SHANGHAI SMARTEE DENTI-TECHNOLOGY CO., LTD.
    Inventors: Huimin Zhuang, Xingxing Wang, Gang Wu, Junfeng Yao