Abstract: A dispersant for a lithium ion battery and a preparation method thereof, a positive slurry, and a lithium ion battery are provided. The dispersant includes a structural unit A derived from N-vinylpyrrolidone, a structural unit B derived from a conjugated diene monomer, and a structural unit C derived from an organic acid monomer. The organic acid monomer includes one or more of an unsaturated sulfonic acid monomer, an unsaturated phosphoric acid monomer, and an unsaturated carboxylic acid monomer.

Abstract: The present invention relates to a fusion protein including an IL15 protein, an IL15 receptor alpha (IL15R?) protein, an Fc domain, and an IL2 protein, and a use thereof, and more specifically, to: a fusion protein including an IL15 protein, an IL15R? protein, an Fc domain, and an IL2 protein; a dimer including the fusion protein; a composition that is for culturing natural killer (NK) cells and includes the fusion protein or dimer; and a method for culturing NK cells. The fusion protein according to the present invention makes it possible to efficiently proliferate and culture NK cells while maintaining the cytolytic activity of the NK cells and promoting the activation of the NK cells when culturing the NK cells, thus making it possible to obtain a large number of NK cells without using feeder cells. Therefore, the fusion protein is useful for the commercialization of NK cells into safe cell therapy agents.

Abstract: A lithium ion electrolyte, a preparation method and application thereof are provided. The lithium ion electrolyte includes: an ester solvent, a lithium salt and an electrolyte additive, where the electrolyte additive includes a compound as shown in the following formula I. According to the electrolyte provided by the present disclosure, all components have a synergistic effect and are matched with one another, so that the electrolyte can improve the interface stability of a high-nickel positive electrode material and prolong the cycle life of a lithium ion battery and a lithium ion capacitor.

Abstract: An optical device is provided. The optical device includes a ring waveguide and a bus waveguide. The ring waveguide includes a coupling region. The bus waveguide is disposed adjacent to and spaced apart from the coupling region of the ring waveguide. The bus waveguide includes a coupling structure corresponding to the coupling region.

Abstract: Embodiments for generating a reservoir performance forecast are provided. The embodiments may be executed by a computer system. In one embodiment, a method includes obtaining inflow performance relationship data generated from a physics-based subsurface-surface coupled simulation model having a surface, a subsurface, and one or more wells fluidly connecting the subsurface to the surface. The inflow performance relationship data comprises performance data for at least one phase of fluid for each well. The method also includes generating a performance forecast for the reservoir using a subsurface simulator and a surface simulator. The subsurface simulator uses the inflow performance relationship data to represent the subsurface during generation of the performance forecast, and the performance forecast satisfies constraints solved by the surface simulator. In one embodiment, a method does not utilize a surface simulator.

Abstract: A semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, a seal ring structure including first and second interconnect structures, and a passivation layer on the seal ring structure and the second dielectric layer. The first interconnect structure is located in the first dielectric layer. The second interconnect structure is located in the second dielectric layer and connected to the first interconnect structure. The passivation layer has a spacer portion covering a sidewall of the second dielectric layer and a portion of the first dielectric layer. A ditch exists in the passivation layer and the first dielectric layer. The spacer portion is located between the ditch and the seal ring structure. The semiconductor structure is able to reduce time and power of an etching process for forming the ditch.

Abstract: A pixel arrangement structure includes: first sub-pixels, second sub-pixels and third sub-pixels, being not overlapped but being spaced apart. The third sub-pixel includes a first edge facing the first sub-pixel, the first sub-pixel includes a second edge facing the third sub-pixel, the third sub-pixel includes a third edge facing the second sub-pixel, and the second sub-pixel includes a fourth edge facing the third sub-pixel, and shapes of the first sub-pixel and the second sub-pixel are circles, the first edge and the second edge are curved edges with a same curvature, the third edge and the fourth edge are curved edges with a same curvature; or shapes of the first sub-pixel and the second sub-pixel are octagons, at least part of the first edge is parallel to at least part of the second edge, at least part of the third edge is parallel to at least part of the fourth edge.

Abstract: A speaker includes: a frame, a vibration system, including a diaphragm, a voice coil, and a flexible circuit board, and a magnetic circuit system, wherein the voice coil includes a first lead wire and a second lead wire, the flexible circuit board includes a first surface facing the diaphragm and a second surface opposite to the first surface, the first lead wire and the first surface are located at one side of the flexible circuit board, the second lead wire and the second surface are located at another side of the flexible circuit board, the flexible circuit board includes a first pad on the first surface and a second pad on the second surface, the first lead wire is connected to the first pad, the second lead wire is connected to the second pad. Compared with the related art, the speaker disclosed by the present disclosure has better acoustic performance.

Abstract: The present disclosure relates to the field of wireless communications, and provides a transmitter switching method, a terminal, a base station, a communication system, a transmitter switching apparatus, and a non-transitory computer readable storage medium. The transmitter switching method includes: a base station sends radio resource control extended signaling to a terminal to instruct a transmitter of the terminal to enter a working mode of time division switching between uplink frequency bands, at least one uplink frequency band having multiple uplink carriers; and the base station sends physical downlink control channel scheduling information to the terminal to instruct the transmitter of the terminal to transmit an uplink frequency band used by uplink data.

Abstract: Dynamic grants (DG) for retransmission by a user equipment (UE) use the communication resource more efficiently while configured grants (CG) for retransmission by the UE reduce overhead and latency. A base station (BS) uses radio resource control signaling to configure the UE with a retransmission timer or without a retransmission timer. The BS transmits to the UE a set of CG configurations configuring a set of configured grant uplink (CG-UL) processes. The set of CG configurations includes information indicating whether or not a cg-RetransmissionTimer is associated with the CG-UL processes. The BS is also configured to receive communication on UL from the UE. The communication from the UE is received based on the set of CG-UL processes and the indication whether or not a cg-RetransmissionTimer is associated with the CG-UL processes.

Abstract: A resistive memory device with an embedded shoulder pulled sidewall spacer and method of forming. The method includes providing a patterned film stack containing a lower electrode layer, a dielectric filament layer on the lower electrode layer, and an upper electrode layer on the dielectric filament layer, depositing a conformal cap layer on the patterned film stack, dry etching the conformal cap layer to form a sidewall spacer on sidewalls of the patterned film stack, where a top of the sidewall spacer is recessed to below a top of the upper electrode layer by the dry etching. The method further includes encapsulating the patterned film stack in an isolation layer, and etching the isolation layer to expose the upper electrode layer without exposing the sidewall spacer.

Abstract: A display device includes a light-emitting pixel and a sensor pixel. The light-emitting pixel includes a light-emitting element, a first transistor electrically connected between a first line and a second line and configured to control a driving current flowing through the light-emitting element in response to a voltage of a first node, and a second transistor connected between the first node and a third line. The sensor pixel includes a light-receiving element connected between a sensor node and the second line, and a first sensor transistor configured to control a current flowing between the third line and a readout line in response to a voltage of the sensor node.

Abstract: A material for forming a blue light-emitting layer, comprising: a main material and a dopant material doped in the main material, wherein there is an overlapping region between the normalized fluorescence emission spectrum of the main material and the normalized absorption spectrum of the dopant material, and the integrated area of the overlapping region is greater than or equal to 50% of the integrated area of the normalized fluorescence emission spectrum of the main material.

Abstract: A sensing device, including a first substrate, a first sensing element, a light-emitting element, and a light-shielding layer, is provided. The first sensing element is located on the first substrate. The light-emitting element is located on the first sensing element. The light-shielding layer is located between the light-emitting element and the first sensing element, and is electrically connected to the light-emitting element.

Abstract: Systems and methods are disclosed for providing a 5G interoperability architecture. In one embodiment, a system is disclosed, comprising: at least one Radio Access network (RAN); at least one core network; and a gateway in communication with the RAN and the core network, the gateway including: a Radio Access Network (RAN) interface for communicating with the at least one RAN; a core network interface for communicating with the at least one core network; and a processor configured to: process 5G signaling received from the at least one RAN on the RAN interface and provide core signaling to at least one core network; and process signaling received from the at least one core on the core network interface and provide 5G RAN signaling to at least one RAN.

Abstract: Method of forming pattern in photoresist layer includes forming photoresist layer over substrate, selectively exposing photoresist layer to actinic radiation forming latent pattern. Latent pattern is developed by applying developer to form pattern. Photoresist layer includes photoresist composition including polymer: A1, A2, L are direct bond, C4-C30 aromatic, C4-C30 alkyl, C4-C30 cycloalkyl, C4-C30 hydroxylalkyl, C4-C30 alkoxy, C4-C30 alkoxyl alkyl, C4-C30 acetyl, C4-C30 acetylalkyl, C4-C30 alkyl carboxyl, C4-C30 cycloalkyl carboxyl, C4-C30 hydrocarbon ring, C4-C30 heterocyclic, —COO—, A1 and A2 are not both direct bonds, and are unsubstituted or substituted with a halogen, carbonyl, or hydroxyl; A3 is C6-C14 aromatic, wherein A3 is unsubstituted or substituted with halogen, carbonyl, or hydroxyl; R1 is acid labile group; Ra, Rb are H or C1-C3 alkyl; Rf is direct bond or C1-C5 fluorocarbon; PAG is photoacid generator; 0<x/(x+y+z)<1, 0<y/(x+y+z)<1, and 0<z/(x+y+z)<1.

Abstract: A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

Abstract: Provided are a drive module, a voltage generation method thereof, and a display device. The drive module includes a mainboard, a power chip, and a driver chip. The driver chip includes a main control unit and a base voltage generation unit. The main control unit is configured to determine the target value of a base voltage in the current drive display mode according to the current drive display mode, determine the optimal voltage multiplying relationship of the base voltage in the current drive display mode according to an analog reference voltage signal and the target value of the base voltage, calculate the actual output value of the base voltage according to the analog reference voltage signal and the optimal voltage multiplying relationship, and generate first instruction information including the actual output value. The base voltage generation unit generates the corresponding base voltage according to the first instruction information.

Abstract: Disclosed are fused imidazole derivatives, preparation methods therefor and medical uses thereof. Specifically, the present disclosure relates to a fused imidazole derivative as shown in general formula (IM), a preparation method therefor, a pharmaceutical composition containing the derivative, and the use of same as a therapeutic agent, in particular the use thereof as a GLP-1 receptor agonist, and the use thereof in the preparation of drugs for the treatment and/or prevention of diabetes.

Abstract: A battery cell, a battery, an electrical apparatus, and a method and a system for manufacturing a battery cell are provided. The battery cell comprises: a case having an opening; an electrode assembly provided within the case; an end cover assembly for closing the opening, wherein the end cover assembly comprises an end cover, an insulating member and a connection adapter member, the end cover is provided with an electrode terminal, and is configured to cover the opening and is connected to the case, the insulating member is provided on one side of the end cover facing the electrode assembly, and the connection adapter member is used for being electrically connected to the electrode terminal and to the electrode assembly; and a buffer member provided on one side of the insulating member facing the electrode assembly.