Abstract: Provided are a system and a method for optimization of network function management and computer readable medium thereof that develop an OAM system architecture compatible with a standard MANO framework set by ETSI, so as to effectively integrate and manage the resources and situation configurations of the network elements (including VNF and CNF) of different manufacturers. Therefore, containment management for various network elements may be flexibly integrated, advantages of the standard MANO framework may be preserved, cost for customized development of various OAM systems and the information transmission therefrom may be reduced, and overall efficiency is increased.

Abstract: In some embodiments, the present disclosure relates to a process tool that includes a lithography apparatus arranged over a wafer chuck and an immersion hood apparatus laterally around the lithography apparatus. The lithography apparatus includes a photomask arranged between a light source and a lens. The immersion hood apparatus comprises input piping, output piping, and extractor piping. The input piping is arranged on a lower surface of the immersion hood apparatus and configured to distribute a liquid between the lens and the wafer chuck. The output piping is arranged on the lower surface of the immersion hood apparatus and configured to contain the liquid arranged between the lens and the wafer chuck. The extractor piping is arranged on an outer sidewall of the immersion hood apparatus and configured to remove any liquid above the wafer chuck that is outside of the immersion hood apparatus.

Abstract: A method includes: providing a workpiece to a semiconductor apparatus, the workpiece including a material layer, wherein the material layer includes a first strip having a first plurality of exposure fields configured to be exposed in a first direction and a second plurality of exposure fields configured to be exposed in a second direction different from the first direction; scanning the first strip along a first scan route in the first direction to generate first topography measurement data; scanning the first strip along a second scan route in the second direction to generate second topography measurement data; and exposing the first plurality of exposure fields according to the first topography measurement data and exposing the second plurality of exposure fields according to the second topography measurement data.

Abstract: In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.

Abstract: A chemical mechanical polishing composition comprises, consists of, or consists essentially of a liquid carrier, anionic particles dispersed in the liquid carrier, an anionic polymer or surfactant, and a cationic polymer.

Abstract: A method for processing a semiconductor wafer is provided. The method includes transferring the semiconductor wafer above a wafer placement device having a plate to align an edge of the semiconductor wafer with a first buffer member positioned in a peripheral region of the plate and to align a center of the semiconductor wafer with a second buffer member positioned in a central region of the plate. Each of the first buffer member and the second buffer member has a stiffness that is less than that of the plate. The method further includes lowering down the semiconductor wafer to place the semiconductor wafer over the plate.

Abstract: In some embodiments, the present disclosure relates to a process tool that includes a lithography apparatus arranged over a wafer chuck and an immersion hood apparatus laterally around the lithography apparatus. The lithography apparatus includes a photomask arranged between a light source and a lens. The immersion hood apparatus comprises input piping, output piping, and extractor piping. The input piping is arranged on a lower surface of the immersion hood apparatus and configured to distribute a liquid between the lens and the wafer chuck. The output piping is arranged on the lower surface of the immersion hood apparatus and configured to contain the liquid arranged between the lens and the wafer chuck. The extractor piping is arranged on an outer sidewall of the immersion hood apparatus and configured to remove any liquid above the wafer chuck that is outside of the immersion hood apparatus.

Abstract: In some embodiments, the present disclosure relates to a process tool that includes a lithography apparatus arranged over a wafer chuck and an immersion hood apparatus laterally around the lithography apparatus. The lithography apparatus includes a photomask arranged between a light source and a lens. The immersion hood apparatus comprises input piping, output piping, and extractor piping. The input piping is arranged on a lower surface of the immersion hood apparatus and configured to distribute a liquid between the lens and the wafer chuck. The output piping is arranged on the lower surface of the immersion hood apparatus and configured to contain the liquid arranged between the lens and the wafer chuck. The extractor piping is arranged on an outer sidewall of the immersion hood apparatus and configured to remove any liquid above the wafer chuck that is outside of the immersion hood apparatus.

Abstract: A near field communication device and a method of determining the position of a tag are provided. The near field communication device includes a first coil, a second coil, and a control circuit. One end of the first coil is coupled to a first grounding end. One end of the second coil is coupled to a second grounding end. The control circuit includes a first current pin and a second current pin. The first current pin is coupled to the other end of the first coil. The second current pin is coupled to the other end of the second coil. The control circuit transmits a first current signal to the first coil by the first current pin, and transmits a second current signal to the second coil by the second current pin, the control circuit analyzes the change of the first current signal and the change of the second current signal to determine whether the position of a tag is close to the first coil or close to the second coil.

Abstract: A method includes providing a first plate including a first surface, a second surface opposite to the first surface, and a first recess indented from the first surface towards the second surface; providing a semiconductor structure including a third surface, a fourth surface opposite to the third surface, and a first sidewall extending between the third surface and the fourth surface; placing the semiconductor structure over the first plate; and disposing a priming material over the third surface of the semiconductor structure, wherein a peripheral portion of the fourth surface of the semiconductor structure is in contact with the first surface of the first plate upon the disposing of the priming material.

Abstract: RF signal amplifiers are provided that include an RF input port, one or more active RF output ports, one or more passive RF output ports, an active communication path, and a passive communication path. Various embodiments include one or more switching devices, one or more directional couplers, one or more diplexers, a power divider network, and/or an attenuator.

Abstract: In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.

Abstract: A cantilever for gas flow direction control configured to support an electrode housing bowl in an associated etch process chamber. The cantilever may have a cross-section that is circular, elliptical, or airfoil shaped. The shape of the cantilever induces the flow of gas and etch products within the chamber around the cantilever, reducing turbulence around the edge of a wafer.

Abstract: A method includes: providing a workpiece to a semiconductor apparatus, the workpiece comprising a material layer, wherein the material layer includes a plurality of areas extending along a first axis; scanning the workpiece in a first direction along the first axis to generate first topography measurement data; scanning the workpiece in a second direction along the first axis to generate second topography measurement data; and performing an exposure operation on the material layer according to the first topography measurement data and the second topography measurement data.

Abstract: A method for forming a layer includes following operations. A workpiece is received in an apparatus for deposition. The apparatus for deposition includes a chamber, a pedestal disposed in the chamber to accommodate the workpiece, and a ring disposed on the pedestal. The ring includes a ring body having a first top surface and a second top surface and a barrier structure disposed between the first top surface and the second top surface. A vertical distance is defined by a top surface of the barrier structure and a top surface of the workpiece. The vertical distance is between approximately 0 mm and approximately 50 mm. A target disposed in the apparatus for deposition is sputtered. A sputtered material is deposited onto a top surface of the workpiece to form a layer. The barrier structure alters an electrical density distribution during the depositing the sputter material.

Abstract: A method includes providing a first plate including a first surface, a second surface opposite to the first surface, and a first recess indented from the first surface towards the second surface; providing a semiconductor structure including a third surface, a fourth surface opposite to the third surface, and a first sidewall extending between the third surface and the fourth surface; placing the semiconductor structure over the first plate; and disposing a priming material over the third surface of the semiconductor structure, wherein a peripheral portion of the fourth surface of the semiconductor structure is in contact with the first surface of the first plate upon the disposing of the priming material.

Abstract: A resist material dispensing system includes a resist supply and a resist filter connected to the resist supply downstream from the resist supply. The resist material dispensing system includes a resist tank structure connected to the resist filter downstream from the resist filter and a resist pump device connected to the resist tank structure downstream from the resist tank structure. The resist tank structure is vertically arranged so that a resist material flows in a continuous downward flow from where the resist material enters the resist tank structure until the resist material exits the resist tank structure.

Abstract: A cooling controller receives, from one or more sensors, wafer information associated with a wafer. The cooling controller determines a pattern mask area for the wafer based on the wafer information. The cooling controller determines a cooling time for the wafer based on the pattern mask area. The cooling controller causes a cooling plate to cool the wafer for a time duration equal to the cooling time. Determining the cooling time for a wafer based on a pattern mask area provides stable and consistent wafer temperatures for wafers having different mask and layout properties, which reduces mask overlay variation and increases wafer yield.

Abstract: A developer tool described herein includes a dispenser that includes a greater quantity of nozzles in a central portion relative to a perimeter portion such that the developer tool is capable of more effectively removing material from a photoresist layer near a center of a substrate (which tends to be thicker near the center of the substrate relative to the edge or perimeter of the substrate). In this way, the developer tool may reduce the amount of photoresist residue or scum remaining on the substrate near the center of the substrate after a development operation, which may enable defect removal and/or prevention, may increase semiconductor processing yield, and/or may increase semiconductor processing quality.

Abstract: A wafer stage includes an area for receiving a wafer. The wafer stage further includes a first sensor outside of the area for receiving the wafer. The wafer stage further includes a second sensor outside of the area of receiving the wafer, wherein the second sensor is spaced from the first sensor. The wafer stage further includes a first particle capture area outside of the area for receiving the wafer, wherein the first particle capture area is spaced from both the first sensor and the second sensor, a dimension of the first particle capture area in a first direction parallel to a top surface of the wafer stage is at least 26 millimeters (mm), a dimension of the first particle capture area in a second direction parallel to the top surface of the wafer stage is at least 33 mm, and the second direction is perpendicular to the first direction.