Patents by Inventor An-Yi Chen

An-Yi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250113539
    Abstract: A method includes forming semiconductive sheets over a substrate and arranged in a vertical direction; forming source/drain regions on either side of each of the semiconductive sheets; forming first air gap inner spacers interleaving with the semiconductive sheets; forming a gate around each of the semiconductive sheets, wherein the first air gap inner spacers are laterally between the gate and a first one of the source/drain regions.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Yi CHOU, Guan-Lin CHEN, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250113499
    Abstract: A semiconductor device including a substrate, a magnetic core and a conductor coil is provided. The magnetic core is disposed on the substrate, and formed by sub-layers of different materials stacked alternatively on one another. The conductor coil is disposed on the substrate, wherein the magnetic core partially extends to a level between an upper surface of the conductor coil and a bottom surface of the conductor coil.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Chi Chiang, Meng-Pei Lu, Shin-Yi Yang, Cian-Yu Chen, Chien-Hsin Ho, Ming-Han Lee, Shau-Lin Shue
  • Publication number: 20250113104
    Abstract: A substation inspection device includes a rack, an anti-vibration mechanism, a camera apparatus and a lock-stop apparatus. The anti-vibration mechanism is mounted on the rack. The camera apparatus includes a first mounting seat and a camera assembly. The first mounting seat is mounted on the rack through the anti-vibration mechanism. The camera assembly is mounted on the first mounting seat. The lock-stop apparatus is mounted on the rack and is configured to fix the camera apparatus.
    Type: Application
    Filed: July 31, 2024
    Publication date: April 3, 2025
    Inventors: Xuefeng NING, Yi RAO, Dexing SUN, Wanwei WANG, Guanke LIU, Xiliang DAI, Rongfu ZHONG, Wei WEI, Zhiqiang LIN, Zehuai LIU, Zhantu YUAN, Long LI, Yuanjia LI, Chuanming TAN, Yongyuan WANG, Dawei LU, Libin QIN, Wenrui CHEN, Haipeng ZHANG
  • Publication number: 20250113538
    Abstract: A semiconductor device includes a substrate, a first active structure, a second active structure, an epitaxy and a conductive via. The first active structure is formed on the substrate and including a plurality of first sheets and a plurality of first spacers. The second active structure is disposed formed on the substrate and adjacent to the first active structure, wherein the second active structure includes a plurality of second sheets and a plurality of second spacers, the second sheets and the second spacers are stacked to each other, and there is trench between the first active structure and the second active structure. The epitaxy is formed within the trench. The conductive via is connected with the epitaxy. The semiconductor device further has a planarized surface including the first active structure, the second active structure and the conductive via, and the planarized surface has a flatness less than 10 nm.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: YI CHEN LIN, Wei-Tse HSU, Ya-Ching TSENG
  • Publication number: 20250113528
    Abstract: Asymmetry may be used to tune electrical properties of tunnel field effect transistors (TFETs). An exemplary TFET includes a gate stack disposed over a semiconductor layer, a source disposed in the semiconductor layer, and a drain disposed in the semiconductor layer. The gate stack includes a gate electrode disposed over a gate dielectric. The gate stack is disposed between the source and the drain. The source has a first conductivity type, and the drain has a second conductivity type different than the first conductivity type. The gate stack is asymmetric. For example, the gate stack has an asymmetric gate dielectric, an asymmetric gate electrode, asymmetric gate footing, asymmetric sidewalls, or combinations thereof. In some embodiments, the source and the drain have asymmetric profiles. In some embodiments, the semiconductor layer is a semiconductor fin, and the gate stack wraps the semiconductor fin.
    Type: Application
    Filed: March 15, 2024
    Publication date: April 3, 2025
    Inventors: Yi-Hong WANG, Yi-Chen LI
  • Publication number: 20250110386
    Abstract: An optical lens module includes an adjustable aperture assembly including rotatable blades, a driving part and an attractive force mechanism. The rotatable blades surround an optical axis of a lens element and form a light pass aperture. The driving part includes a rotatable component, a fixed component, a driving magnet and a coil. The rotatable component rotates the rotatable blades for adjusting an aperture size of the light pass aperture. The driving magnet is disposed on the rotatable component. The coil corresponds to the driving magnet to rotate the rotatable component. The attractive force mechanism provides an attractive force between the rotatable component and the fixed component and provides a driving force exerted on the rotatable blades for maintaining the light pass aperture in an enlarged state. The attractive force includes a magnetic force exerted by the rotatable component on a first magnetic element fixed on the fixed component.
    Type: Application
    Filed: April 22, 2024
    Publication date: April 3, 2025
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Zheng-Zhi HONG, Hsiu-Yi HSIAO, Hao Jan CHEN, Ming-Ta CHOU
  • Publication number: 20250113497
    Abstract: Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.
    Type: Application
    Filed: December 9, 2024
    Publication date: April 3, 2025
    Inventors: Yuan-Sheng Huang, Yi-Chen Chen
  • Publication number: 20250110164
    Abstract: An electrostatic field strength measuring apparatus includes an electrostatic field detection device and a processor. The electrostatic field detection device includes a ring light source configured to emit a light signal to a target object, and a reflection detector disposed within and surrounded by the ring light source and configured to receive a reflection signal, of the light signal, reflected by a surface of the target object and generate an electrical signal based upon the reflection signal. The processor is configured to determine, based upon the electrical signal, measures of electrostatic field strength at the surface of the target object.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Da Yang, Chun-Hsuan Lin, Yi-Chen Li
  • Publication number: 20250111013
    Abstract: Provided are an information generation method and apparatus, and an electronic device.
    Type: Application
    Filed: January 3, 2023
    Publication date: April 3, 2025
    Inventors: Xiaoming GAO, Qin LIU, Huihong LI, Fang CHEN, Shidi LIU, Yi YAN, Cong MAI, Jinming ZENG, Yunzhi LIU, Wenhao TAN, Guangwen CAI, Huiying DENG, Xiaoming XU, Yunbin SU, Xueming JIANG, Liyou ZHANG, Mingyi GUO, Jiechao LIAO, Xuehao LI
  • Publication number: 20250108129
    Abstract: Compositions for use in treating subjects with USH2A-associated retinal and/or cochlear disease that result from mutations in exon 13 of the USH2A gene by deletion of exon 13 splicing acceptor sequences from the USH2A gene or transcripts, and methods of use thereof, as well as genetically modified animals and cells.
    Type: Application
    Filed: February 3, 2023
    Publication date: April 3, 2025
    Inventors: Zheng-Yi Chen, Wenliang Zhu
  • Publication number: 20250110291
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a bottom package having a first sidewall and a second sidewall opposite to each other; a hybrid path layer disposed on the bottom package, wherein the hybrid path layer comprises an optical path layer and an electrical path layer, and at least one optical path of the optical path layer extends from the first sidewall of the bottom package beyond a center of the bottom package; and a plurality of dies bonded onto the hybrid path layer.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Yu-Hao Chen, Hao-Yi Tsai, An-Jhih Su, Tzuan-Horng Liu, Po-Yuan Teng, Tsung-Yuan Yu, Che-Hsiang Hsu
  • Publication number: 20250110596
    Abstract: A display panel is provided. The display panel includes a touch control structure. The touch control structure includes a plurality of first mesh electrodes and a plurality of second mesh electrodes. A respective one of the plurality of first mesh electrodes includes a plurality of first mesh blocks consecutively electrically connected along a first direction. A respective one of the plurality of second mesh electrodes includes a plurality of second mesh blocks consecutively electrically connected along a second direction. Two adjacent second mesh blocks of the plurality of second mesh blocks are electrically connected to each other through a respective second conductive bridge. The respective second conductive bridge includes a plurality of second single mesh lines spaced apart from each other, and in a same layer as the plurality of first mesh blocks and the plurality of second mesh blocks.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yang Zeng, Tianci Chen, Shun Zhang, Chang Luo, Yuanqi Zhang, Yi Zhang, Youngyik Ko, Sanghun Kang
  • Publication number: 20250112175
    Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Brandon C. Marin, Jesse C. Jones, Yosef Kornbluth, Mitchell Page, Soham Agarwal, Fanyi Zhu, Shuren Qu, Hanyu Song, Srinivas V. Pietambaram, Yonggang Li, Bai Nie, Nicholas Haehn, Astitva Tripathi, Mohamed R. Saber, Sheng Li, Pratyush Mishra, Benjamin T. Duong, Kari Hernandez, Praveen Sreeramagiri, Yi Li, Ibrahim El Khatib, Whitney Bryks, Mahdi Mohammadighaleni, Joshua Stacey, Travis Palmer, Gang Duan, Jeremy Ecton, Suddhasattwa Nad, Haobo Chen, Robin Shea McRee, Mohammad Mamunur Rahman
  • Publication number: 20250112136
    Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
  • Publication number: 20250112353
    Abstract: A liquid crystal antenna includes a first substrate, a second substrate oppositely arranged to the first substrate, a plurality of first conductive parts located over one side of the first substrate adjacent to the second substrate, a plurality of second conductive parts located over one side of the second substrate adjacent to the first substrate, a third substrate, a plurality of third conductive parts located over one side of the third substrate away from the second substrate, a liquid crystal layer, and a frame adhesive located between the first substrate and the second substrate. The third substrate is positioned over one side of the second substrate away from the first substrate, at least one side surface of the second substrate, and the side of the second substrate adjacent to the first substrate.
    Type: Application
    Filed: August 6, 2024
    Publication date: April 3, 2025
    Inventors: Qingsan ZHU, Yifan XING, Baiquan LIN, Kerui XI, Ping SU, Ximin QI, Qiang SUN, Jiayun CHEN, Yi WANG
  • Publication number: 20250112200
    Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Kimin Jun, Feras Eid, Thomas Sounart, Yi Shi, Shawna Liff, Johanna Swan, Michael Baker, Bhaskar Jyoti Krishnatreya, Chien-An Chen
  • Patent number: 12266573
    Abstract: In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a second semiconductor fin protruding above the isolation region; and a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin protruding above the isolation region, the dielectric fin including: a first layer including a first dielectric material having a first carbon concentration; and a second layer on the first layer, the second layer including a second dielectric material having a second carbon concentration, the second carbon concentration greater than the first carbon concentration.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Chen Ho, Yiting Chang, Chi-Hsun Lin, Zheng-Yang Pan
  • Patent number: 12267462
    Abstract: Implementations relate to determination and display of estimated hold durations for calls. In some implementations, a computer-implemented method includes obtaining an identifier of a target entity, the identifier usable by a first call device to initiate a call between the first call device and the target entity. A hold duration is determined that is an estimated amount of time before the call is matched to a human agent when the call is initiated at a particular time that is prospective to a current time. The hold duration is determined based on previous calls between one or more call devices and the target entity. The hold duration is provided for display by the first call device prior to the initiation of the call between the first call device and the target entity.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: April 1, 2025
    Assignee: Google LLC
    Inventors: Joseph Joseph Cherukara, Hong Chen, Andrew George Shebanow, Rebecca Chiou, Yixuan Geng, Curtis Ray Robinson, Jr., Yi Wang, Yue Gan, Charlotte Hult, Bin Sun
  • Patent number: 12265635
    Abstract: A method enhances authentication requirements to documents of a document repository based, at least in part, on a security policy associated with a branch under which the documents are organized. The method implements an approval service that is identified in a branch policy. The approval service determines whether a user is authorized to modify documents included in the branch. The method further selectively requires multiple authentications from multiple authentication systems in order to access one or more particular branches in a document repository. Further, the multiple authentication systems are based on separate and independent sets of authentication credentials.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: April 1, 2025
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Filip Sebesta, Yu Lin Sie, Yi Zeng, Lingxia Chen
  • Patent number: 12264106
    Abstract: A cerium-zirconium-aluminum-based composite material, a cGPF catalyst and a preparation method thereof are provided. The cerium-zirconium-aluminum-based composite material adopts a stepwise precipitation method, firstly preparing an aluminum-based pre-treated material, then coprecipitating the aluminum-based pre-treated material with zirconium and cerium sol, and finally roasting at high temperature to obtain the cerium-zirconium-aluminum-based composite material. The cerium-zirconium-aluminum-based composite material has better compactness and higher density, and when it is used in cGPF catalyst, it occupies a smaller volume of pores on the catalyst carrier, such that cGPF catalyst has lower back pressure and better ash accumulation resistance, which is beneficial to large-scale application of cGPF catalyst.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: April 1, 2025
    Assignee: SINOTECH COMPANY LIMITED
    Inventors: Dacheng Li, Jinfeng Wang, Li Lan, Hui Ye, Lan Yang, Feng Zhang, Yi Yang, Yongxiang Cheng, Tiantian Luo, Yinhua Dong, Yun Wang, Yun Li, Qizhang Chen