Patents by Inventor An-Yu Kuo

An-Yu Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10803222
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify connectivity of an electronic design that includes an embedded circuit, and the embedded circuit is located between a first actual layer and a second actual layer of the electronic design. The electronic design is then transformed, but one or more embedded circuit modules, into a transformed electronic design at least by generating one or more artificial interconnects between the embedded circuit and a plurality of metal patches. The connectivity may be re-established based at least in part upon the plurality of metal patches. The electronic design may then be implemented based at least in part upon predicted behaviors of the transformed electronic design.
    Type: Grant
    Filed: September 30, 2018
    Date of Patent: October 13, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jian Liu, Karthikeyan Mahadevan, An-Yu Kuo
  • Patent number: 10762260
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify a specification of an electronic design, a parameter for optimization, at least one optimization target for the parameter, and initial grids for the electronic design. An optimization map may be determined, by at one or more optimization modules that are stored at least partially in memory of and function in conjunction with at least one microprocessor of a computing system, for the electronic design at least by performing one or more analyses that refine the initial grids for the optimization map with respect to the parameter and the at least one optimization target. The electronic design may be implemented based at least in part upon the optimization map.
    Type: Grant
    Filed: September 30, 2018
    Date of Patent: September 1, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jian Liu, Jing Wang, Chun-Teh Kao, An-Yu Kuo
  • Patent number: 10685166
    Abstract: Various techniques implement an electronic design with physical simulations using layout artwork. The approximate behaviors of the electronic design are determined. A region in the electronic design is identified. A first three-dimensional model is identified, if pre-existing, or generated, if non-existing, for the region in the electronic design. The behaviors of the region is determined using at least physics-based techniques or methodologies that are preconditioned upon at least a portion of the approximate behaviors determined for the electronic design.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 16, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chun-Teh Kao, An-Yu Kuo
  • Patent number: 10380293
    Abstract: Disclosed are techniques for implementing physics aware model reduction for a design. These techniques identify a design model and generate a first set of solutions with a first discretization scheme and a plurality of inputs. A second discretization scheme may be generated at least by performing geometry simplification and re-discretization based in part or in whole on one or more distributions from the first set of solution. With the second discretization scheme, a second set of solutions may be generated with the second discretization scheme and the plurality of inputs.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: August 13, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jian Liu, Mazen Issam Baida, Mingjin Zhang, An-Yu Kuo
  • Patent number: 9910947
    Abstract: The described techniques implement electronic designs with thermal analyses of the electronic design and its surrounding medium by performing thermal modeling that determines at least a thermal RC network for an electronic design. These techniques further generate a thermal network for the electronic design and one or more surrounding media of the electronic design and generate or modify the electronic design with an implementation process at least by guiding the implementation process based in part or in whole upon results of performing one or more thermal analysis on the thermal network.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 6, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chun-Teh Kao, An-Yu Kuo
  • Patent number: 9864827
    Abstract: The present disclosure relates to a system and method for modeling an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design. Embodiments may also include partitioning, at a graphical user interface configured to display at least a portion of the electronic circuit design, at least one portion of the electronic circuit design into one or more sub-zones and generating, at the graphical user interface, one or more ports at each interface between one or more sub-zones. Embodiments may further include receiving a selection for an electromagnetic (EM) solver for each of the one or more sub-zones. Embodiments may also include modeling each of the one or more sub-zones.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: January 9, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jilin Tan, Jian Chen, Jian Liu, An-Yu Kuo, Tiejun Yu
  • Patent number: 9785141
    Abstract: Disclosed are methods and systems for by identifying or generating an electrical schematic, generating a thermal schematic by associating thermal RC circuits of the electronic design with the electrical schematic, performing at least two analyses of an electrical analysis, a thermal analysis, and an electromagnetic interference compliance (EMC) analysis with the electrical schematic and the thermal schematic of the electronic design. The electrical, thermal, and EMC analyses may be performed concurrently by forwarding intermediate or final analysis results to each other, and the analysis results may be presented simultaneously in one or more user interface windows. The thermal schematic may be obtained by extracting the thermal RC circuits, identifying corresponding electrical circuit components that correspond to the extracted thermal RC circuits, and importing the thermal RC circuits into the electrical schematic so that the electrical and thermal schematics have the same nodes.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: October 10, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Alok Tripathi, An-yu Kuo, Bradley Brim, Taranjit Singh Kukal
  • Patent number: 9672319
    Abstract: Disclosed are techniques for model-based electronic design implementation with a hybrid solver. These techniques generate an extruded via from a linkage node to a reference metal plane that is added to an analysis model for at least a portion of an electronic design. The analysis model for the at least the portion is generated at least by re-establishing interconnection between the at least the portion and a linkage circuit element with the extruded via. At least the portion of the electronic design may further be implemented using the analysis or simulation results that are generated by using the hybrid solver on the model, without using three-dimensional solvers, for a three-dimensional model of the electronic design.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 6, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Xiande Cao, Jian Liu, An-yu Kuo
  • Publication number: 20160063171
    Abstract: Disclosed are methods and systems for by identifying or generating an electrical schematic, generating a thermal schematic by associating thermal RC circuits of the electronic design with the electrical schematic, performing at least two analyses of an electrical analysis, a thermal analysis, and an electromagnetic interference compliance (EMC) analysis with the electrical schematic and the thermal schematic of the electronic design. The electrical, thermal, and EMC analyses may be performed concurrently by forwarding intermediate or final analysis results to each other, and the analysis results may be presented simultaneously in one or more user interface windows. The thermal schematic may be obtained by extracting the thermal RC circuits, identifying corresponding electrical circuit components that correspond to the extracted thermal RC circuits, and importing the thermal RC circuits into the electrical schematic so that the electrical and thermal schematics have the same nodes.
    Type: Application
    Filed: September 3, 2014
    Publication date: March 3, 2016
    Applicant: Cadence Design Systems, Inc.
    Inventors: Alok Tripathi, An-yu Kuo, Bradley Brim, Taranjit Singh Kukal
  • Patent number: 8880386
    Abstract: A computer-implemented method for simulating an electrical circuit. The method includes (a) setting a first temperature distribution in the electrical circuit, (b) performing an electrical simulation across the electrical circuit taking into consideration the first temperature distribution, (c) performing a thermal simulation across the electrical circuit taking into consideration a result of the electrical simulation, to obtain a second temperature distribution, and (d) determining whether a criterion for termination the simulation is met. If the criterion is met, terminate the simulation. If the criterion is not met, assign the second temperature distribution to the first temperature distribution, and repeat steps (b), (c), and (d).
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: November 4, 2014
    Assignee: Sigrity, Inc.
    Inventors: An-Yu Kuo, Xin Al
  • Publication number: 20120316857
    Abstract: A computer-implemented method for simulating an electrical circuit. The method includes (a) setting a first temperature distribution in the electrical circuit, (b) performing an electrical simulation across the electrical circuit taking into consideration the first temperature distribution, (c) performing a thermal simulation across the electrical circuit taking into consideration a result of the electrical simulation, to obtain a second temperature distribution, and (d) determining whether a criterion for termination the simulation is met. If the criterion is met, terminate the simulation. If the criterion is not met, assign the second temperature distribution to the first temperature distribution, and repeat steps (b), (c), and (d).
    Type: Application
    Filed: June 13, 2011
    Publication date: December 13, 2012
    Inventors: An-Yu Kuo, Xin Ai
  • Publication number: 20050197808
    Abstract: A method for determining electrical and magnetic field effects determines Lanczos matrices by performing a preconditioned conjugate gradient method using a nested multi-grid, vector and scalar potential preconditioner so that Pade via Lanczos frequency expansion may be used to determine the electrical and magnetic field effects over a frequency range without having to perform computationally slow and memory intensive matrix decomposition.
    Type: Application
    Filed: March 7, 2005
    Publication date: September 8, 2005
    Inventor: An-Yu Kuo