Patents by Inventor An-Yu Yen

An-Yu Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230411209
    Abstract: A method for manufacturing a semiconductor device includes: forming a patterned mask on a patterned structure disposed on a substrate, such that a first mask portion and a second mask portion of the patterned mask are disposed on a first interconnect feature and a second interconnect feature of the patterned structure, respectively; and subjecting the patterned mask to a plasma treatment process such that the first and second mask portions are deformed to form a capping portion to cap a recess disposed between the first and second interconnect features so as to form an air gap.
    Type: Application
    Filed: June 16, 2022
    Publication date: December 21, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Yu YEN, Keng-Chu LIN
  • Publication number: 20230400708
    Abstract: A contact lens is provided and includes a lens body and an embedded structure embedded in the lens body. The lens body includes a cornea portion and a sclera portion surrounding the cornea portion, and a connection boundary between the cornea portion and the sclera portion has an inner diameter within a range from 11.5 mm to 12.3 mm. The cornea portion defines a layout boundary spaced apart from the connection boundary by a distance within a range from 3.8 mm to 4.2 mm. The embedded structure is arranged outside of the layout boundary, and has a three-dimensional (3D) carrier. The 3D carrier has at least one oxygen permeable channel having a central angle of 360 degrees. Along a top-down direction, at most 70% of an area of an annular layout region between the layout boundary and the connection boundary is shielded by the embedded structure.
    Type: Application
    Filed: May 17, 2023
    Publication date: December 14, 2023
    Inventors: TE-SHENG YANG, HAN-YI CHANG, WEI-JIA TING, YU-YEN CHIANG, YI-FANG HUANG
  • Publication number: 20230387312
    Abstract: A method is provided for forming a semiconductor device. A fin feature is formed on a semiconductor substrate, and a dummy gate feature is formed over the fin feature. The fin feature includes a sacrificial portion disposed over the semiconductor substrate, and a fin portion disposed over the sacrificial portion. The dummy gate feature is connected to the fin feature and the semiconductor substrate. Then, the sacrificial portion is removed to form a gap between the semiconductor substrate and the fin portion. A dielectric isolation layer is formed to fill the gap for electrically isolating the fin portion from the semiconductor substrate. Subsequently, source/drain features are formed over the dielectric isolation layer, and the dummy gate feature is processed to form a gate electrode feature on the fin portion.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Yu YEN, Wei-Ting YEH, Ko-Feng CHEN, Keng-Chu LIN
  • Patent number: 11828646
    Abstract: Herein disclosed is an optoelectronic unit measuring device comprising an objective lens, an imaging lens, a photographing lens, and a focus adjustment module disposed in a first light path. The objective lens receives a first testing light and converts the first testing into a second testing light. The imaging lens receives the second testing light and converts the second testing light into a third testing light. The photographing lens receives the third testing light and measures beam characteristic. The focus adjustment module selectively provides a first light transmitting member in the first light path, and adjusts the third testing light to focus at a first focus position or a second focus position. Wherein the focus adjustment module comprises a first carrier plate having a first area with the first light transmitting member, and moves the first carrier plate to selectively align the first area with the first light path.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: November 28, 2023
    Assignee: CHROMA ATE INC.
    Inventors: Yu-Yen Wang, Kuo-Wei Huang, Szu-Yuan Weng
  • Patent number: 11832435
    Abstract: A method of fabricating the semiconductor device includes forming a bit line structure over a substrate, forming a spacer structure on a sidewall of the bit line structure, partially removing an upper portion of the spacer structure to form a slope on the spacer structure slanting to the bit line structure, forming a landing pad material to cover the spacer structure and contact the slope, and removing at least a portion of the landing pad material to form a landing pad against the slope.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: November 28, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Wei Huang, Hsu-Cheng Fan, En-Jui Li, Chih-Yu Yen
  • Publication number: 20230364552
    Abstract: The invention provides a low-temperature hydrogen oxidation system comprising at least one hydrogen oxidation device, at least one hydrogen reaction module is disposed in the hydrogen oxidation device, at least one hydrogen reaction channel is formed in the hydrogen reaction module and is provided with at least one catalyst, the hydrogen oxidation device is provided with at least one gas inlet channel and at least one gas outlet channel to communicate with the hydrogen reaction channel, at least one cooling channel is further formed in the hydrogen oxidation device; and at least one gas humidifying device disposed at a position of the gas inlet channel.
    Type: Application
    Filed: August 24, 2022
    Publication date: November 16, 2023
    Inventors: Ming-Yu Yen, HSU-LIN CHANG, FU-YANG SHIH
  • Publication number: 20230333327
    Abstract: The present disclosure relates to a method of making a lensed connector in which a glass ferrule has holes within the body of the glass ferrule, and the glass ferrule is subsequently processed to form lens structures along the ferrule.
    Type: Application
    Filed: June 22, 2023
    Publication date: October 19, 2023
    Inventors: Nicholas Francis Borrelli, Davide Domenico Fortusini, Yu-Yen Huang, Shawn Michael O'Malley, Georges Roussos, Joseph Francis Schroeder, III, Jun Yang, Lei Yuan
  • Publication number: 20230317585
    Abstract: A package structure includes a first redistribution circuit structure, a semiconductor die, a connecting film, and a second redistribution circuit structure. The first redistribution circuit structure includes a dielectric structure and a routing structure disposed therein, where the dielectric structure includes a trench exposing the routing structure. The semiconductor die is disposed on and electrically coupled to the first redistribution circuit structure. The connecting film is disposed in the trench and between the semiconductor die and the first redistribution circuit structure, and the semiconductor die is thermally coupled to the routing structure through the connecting film.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Wei-Jhan Tsai, Sheng-Feng Weng, Ching-Yao Lin, Ming-Yu Yen, Kai-Fung Chang, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20230260961
    Abstract: A semiconductor package includes a first substrate and a first semiconductor device. The first semiconductor device is bonded to the first substrate and includes a second substrate, a plurality of first dies and a second die. The first dies are disposed between the first substrate and the second substrate. The second die is surrounded by the first dies. A cavity is formed among the first dies, the first substrate and the second substrate, and a gap is formed between the second die and the first substrate.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Fung Chang, Sheng-Feng Weng, Ming-Yu Yen, Chih-Wei Lin, Ching-Hua Hsieh
  • Patent number: 11722423
    Abstract: Disclosed is a data flow classification device including a forwarding circuit and a configuring circuit. The forwarding circuit looks the classification of an input flow up in a lookup table according to the information of the input flow, tags the packets of the input flow with the classification, and outputs the packets to a buffer circuit. The configuring circuit receives and stores the identification and traffic information of multiple flows, and accordingly calculates the traffic of the multiple flows, wherein the multiple flows include the input flow. The configuring circuit further determines an elephant flow threshold according to a queue length of the buffer circuit and a target length, determines the classifications of the multiple flows according to the comparison between the traffic of the multiple flows and the elephant flow threshold, and stores these classifications in the lookup table.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: August 8, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kuo-Cheng Lu, Min-Chang Wei, Chun-Ming Liu, Kuang-Yu Yen
  • Patent number: 11719891
    Abstract: The present disclosure relates to a method of making a lensed connector in which a glass ferrule has holes within the body of the glass ferrule, and the glass ferrule is subsequently processed to form lens structures along the ferrule.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: August 8, 2023
    Assignee: Corning Research & Development Corporation
    Inventors: Nicholas Francis Borrelli, Davide Domenico Fortusini, Yu-Yen Huang, Shawn Michael O'Malley, Georges Roussos, Joseph Francis Schroeder, III, Jun Yang, Lei Yuan
  • Publication number: 20230241679
    Abstract: Reactor configurations may include one or more staged inlets and/or one or more staged outlets for gaseous and solid feedstocks. In one embodiment of the present disclosure, a reactor design for gas-solid reaction with one or more additional outlet for gas and/or solid phase is provided. In yet another embodiment, the design for a gas-solid reactor with one side inlet and two outlets for gas phase is described. In one embodiment, a reactor design with pairs of inlet and outlet for both gas and solid phase is provided. In another embodiment, a reactor design with one or more side inlets but only one outlet for gas phase is provided. In yet another embodiment, a reactor design with two inlets at the top/bottom of reactor and two side outlets for gaseous phase is described. In yet another embodiment, a reactor design with one or more side inlets and outlets for both gas and solid phases is provided.
    Type: Application
    Filed: June 29, 2021
    Publication date: August 3, 2023
    Inventors: Liang-Shih Fan, Andrew Tong, Liang Zeng, Yitao Zhang, Frank Kong, Yu-Yen Chen
  • Publication number: 20230213575
    Abstract: A scan chain designing method includes: obtaining test points according to a gate-level netlist; determining integers M and N, wherein M and N are no greater than an amount X of the test points; selecting M and N test points to be a first and second set test points according to a priority; obtaining a first test coverage and a first test pattern count according to the first set test points and obtaining a second test coverage and a second test pattern count according to the second set test points; obtaining a predicted test coverage curve according to the first and second test coverages; determining an optimum amount O according to the predicted test coverage curve, the first and second test pattern counts, wherein O is no greater than X; and selecting O test points to arrange a scan chain according to the priority and the optimum amount O.
    Type: Application
    Filed: October 25, 2022
    Publication date: July 6, 2023
    Inventors: SHIOU WEN WANG, YU YEN YANG, YING-YEN CHEN
  • Publication number: 20230202774
    Abstract: A method for automatically placing a to-be-packed object into a container that defines an accommodation space is provided. A processing unit obtains an object dimension data piece that indicates dimensions of the to-be-packed object, and obtains, through a camera unit that captures images of the to-be-packed object and the accommodation space, an unoccupied area related to the accommodation space. Based on the object dimension data piece and the unoccupied area, the processing unit determines whether the container is capable of accommodating the to-be-packed object.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Cheng-Lung CHEN, Xuan Loc NGUYEN, Ting Han LIU, Yu-Yen LIU
  • Patent number: 11673116
    Abstract: The present invention relates to a superabsorbent polymer and a method for producing the same. The superabsorbent polymer includes a core layer polymerized with monomers having carboxylic group, a first shell layer formed from a surface crosslinking agent, and a second shell layer formed from zingiberaceae extracts. By a surface modification on the first shell layer performed from a specific amount of the zingiberaceae extracts, the superabsorbent polymer produced according to the method for producing the same has a good antimicrobial property and deodorizing effects, and retains an original absorbent property.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: June 13, 2023
    Assignee: FORMOSA PLASTICS CORPORATION
    Inventors: Zhong-Yi Chen, Cheng-Lin Lee, Feng-Yi Chen, Yu-Yen Chuang
  • Publication number: 20230178593
    Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a sacrificial base layer over a substrate and forming a semiconductor stack over the sacrificial base layer. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack to partially cover the sacrificial base layer, the semiconductor layers, and the sacrificial layers. The method further includes removing the sacrificial base layer to form a recess between the substrate and the semiconductor stack. In addition, the method includes forming a metal-containing dielectric structure to partially or completely fill the recess. The metal-containing dielectric structure has multiple sub-layers.
    Type: Application
    Filed: June 6, 2022
    Publication date: June 8, 2023
    Inventors: Wei-Ting Yeh, Hung-Yu Yen, Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 11656604
    Abstract: Provided is a cutting speed planning system including a graphic preprocessing engine, a first speed planning engine, an included angle calculation engine, a second speed planning engine and a speed determination engine. The graphic preprocessing engine substitutes a simplified cutting route for a plurality of short straight paths of a graphic path. The first speed planning engine calculates a reasonable maximum cutting speed of each cutting route. The included angle calculation engine calculates the included angle between two adjacent ones of the cutting routes. The second speed planning engine adjusts the terminal cutting speed and the initial cutting speed of the cutting routes. The speed determination engine performs speed planning on the cutting routes according to digital control system period time. A cutting speed planning method and a non-transitory storage medium are further provided.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: May 23, 2023
    Assignee: ADLINK TECHNOLOGY INC.
    Inventors: Wei-Li Chuang, Wei-Fan Chen, Yu-Yen Chen
  • Publication number: 20230157001
    Abstract: A method of fabricating the semiconductor device includes forming a bit line structure over a substrate, forming a spacer structure on a sidewall of the bit line structure, partially removing an upper portion of the spacer structure to form a slope on the spacer structure slanting to the bit line structure, forming a landing pad material to cover the spacer structure and contact the slope, and removing at least a portion of the landing pad material to form a landing pad against the slope.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 18, 2023
    Inventors: Chih-Wei HUANG, Hsu-Cheng FAN, En-Jui LI, Chih-Yu YEN
  • Publication number: 20230124939
    Abstract: An optical lens assembly is adapted for receiving a light beam that is emitted by an object, and includes a lens unit and a sleeve unit. The lens unit includes a casing that has a light-incident side adapted for receiving the light beam. The sleeve unit surrounds the light-incident side of the casing, and defines a light-receiving space that is adapted for the light beam to pass through so that propagation of the light beam is unaffected by disturbance caused by movement of air. An optical measurement method includes steps of: a) providing a lens unit, a sleeve unit, and an object that is for emitting a light beam; and b) operating the lens unit so that the light beam is received by the lens unit.
    Type: Application
    Filed: October 4, 2022
    Publication date: April 20, 2023
    Inventors: Kuo-Wei HUANG, Hung-Ta KAO, Po-Chen KANG, Szu-Yuan WENG, Yu-Yen WANG
  • Patent number: 11632824
    Abstract: A method for verifying whether a candidate peer functions as a mesh gate is performed by a network device in a mesh basic service set including the candidate peer. The method includes: providing a record indicates that the candidate peer doesn't function as the mesh gate, when the network device receives a notification from the candidate peer indicating that the candidate peer now functions as the mesh gate, having the network device update the record and start a counting process and verifying whether the candidate peer continues functioning as the mesh gate till the end of the counting process; when the network device doesn't receive an updated notification from the candidate peer indicating that the candidate functions as the mesh gate before the end of the counting process, having the network device send a packet to the candidate peer to verify whether the candidate peer functions as the mesh gate.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: April 18, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chia-Feng Hung, Shun-Yin Chiu, Yu-Yen Ting