Patents by Inventor An YU

An YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12078180
    Abstract: A centrifugal compressor and a refrigerating device. The centrifugal compressor includes: a shell, which has a fluid inlet and a fluid outlet; a motor assembly including a stator and a rotor, the rotor including a vertically arranged rotor shaft; a centrifugal compression mechanism, an impeller of which is connected with the rotor shaft so as to be driven by the motor assembly, wherein the centrifugal compression mechanism is arranged downstream of the fluid inlet to receive fluid, compress and pressurize the fluid, and output the pressurized fluid in a direction away from the motor assembly; and a guide member, which receives the pressurized fluid from the centrifugal compression mechanism, and which defines a flow passage alone or together with a part of the shell, wherein the flow passage is configured such that the pressurized fluid from the centrifugal compression mechanism passes through and cools the motor assembly.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: September 3, 2024
    Assignee: CARRIER CORPORATION
    Inventors: Tingcan Mi, Kai Deng, Lei Yu, Guangyu Shen, Fei Xie, Yuhui Kuang
  • Patent number: 12081481
    Abstract: Provided are a signaling sending method and device and a signaling receiving method and device. The signaling sending method includes: configuring N sets according to reference-signal-related information satisfying a predetermined channel characteristic requirement, where N is an integer greater than or equal to 1, and an element in the N sets is the reference-signal-related information; generating a first type of signaling, where the first type of signaling carries the N sets; and sending the first type of signaling to a second communication node, where the first type of signaling is used for notifying the second communication node to perform beam indication according to the N sets.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: September 3, 2024
    Assignee: ZTE Corporation
    Inventors: Bo Gao, Yu Ngok Li, Zhaohua Lu, Yifei Yuan, Xinhui Wang
  • Patent number: 12080006
    Abstract: Systems and methods for classifying at least a portion of an image as being textured or textureless are presented. The system receives an image generated by an image capture device, wherein the image represents one or more objects in a field of view of the image capture device. The system generates one or more bitmaps based on at least one image portion of the image. The one or more bitmaps describe whether one or more features for feature detection are present in the at least one image portion, or describe whether one or more visual features for feature detection are present in the at least one image portion, or describe whether there is variation in intensity across the at least one image portion. The system determines whether to classify the at least one image portion as textured or textureless based on the one or more bitmaps.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: September 3, 2024
    Assignee: MUJIN, INC.
    Inventors: Jinze Yu, Jose Jeronimo Moreira Rodrigue, Ahmed Abouelela
  • Patent number: 12075715
    Abstract: The present disclosure relates to a transmission of an agricultural vehicle, the transmission including: a forward shift unit for performing shift with respect to drive transmitted from an engine of an agricultural vehicle; a clutch unit connected to the forward shift unit so as to selectively output drive transmitted from the forward shift unit; an adjustment unit connected to the clutch unit; and a backward shift unit connected to the adjustment unit so as to perform shift with respect to drive transmitted from the adjustment unit. The adjustment unit includes: a first adjustment mechanism connected to a first clutch mechanism included in the clutch unit; a second adjustment mechanism connected to a second clutch mechanism included in the clutch unit; and an integration mechanism connected to both the first adjustment mechanism and the second adjustment mechanism. The backward shift unit includes one backward shift mechanism connected to the integration mechanism.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: September 3, 2024
    Assignee: LS MTRON LTD.
    Inventors: Jung Su Han, Won Woo Park, Ji Hun Yu, Taek Seong Kim, Young Gyu Lee, Jae Gone Kim
  • Patent number: 12076677
    Abstract: A method for collecting dust from a single crystal growth system includes providing dry air and oxygen into an exit pipe connecting to the single crystal growth system, blowing a first inert gas into the exit pipe to compel the dust oxide toward a dust collecting device, collecting the dust oxide by the dust collecting device; and providing a rotary pump to transport residues of the dust oxide backward. The oxygen reacts with the unstable dust for forming dust oxide. The exit pipe is used to exhaust unstable dust from the single crystal growth system.
    Type: Grant
    Filed: July 3, 2023
    Date of Patent: September 3, 2024
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Masami Nakanishi, Yu-Sheng Su, I-Ching Li
  • Patent number: 12076398
    Abstract: An anti-PDl (programmed cell death 1) monoclonal antibody or an antigen-binding fragment thereof, a pharmaceutical composition thereof and use thereof. The heavy chain variable region of the monoclonal antibody comprises CDRs (complementary determining region) of amino acid sequences as shown in SEQ ID NO:9-11; and/or the light chain variable region of the monoclonal antibody comprises CDRs of amino acid sequences as shown in SEQ ID NO: 12-14. The monoclonal antibody can bind to PDl specifically, relieve immunosuppression of PDl on an organism specifically and activate T lymphocytes.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: September 3, 2024
    Assignee: CTTQ-AKESO (SHANGHAI) BIOMED. TECH. CO., LTD.
    Inventors: Baiyong Li, Yu Xia, Zhongmin Maxwell Wang, Peng Zhang
  • Patent number: 12079341
    Abstract: In one embodiment, an apparatus comprises a processor to: receive a request to configure a secure execution environment for a first workload; configure a first set of secure execution enclaves for execution of the first workload, wherein the first set of secure execution enclaves is configured on a first set of processing resources, wherein the first set of processing resources comprises one or more central processing units and one or more accelerators; configure a first set of secure datapaths for communication among the first set of secure execution enclaves during execution of the first workload, wherein the first set of secure datapaths is configured over a first set of interconnect resources; configure the secure execution environment for the first workload, wherein the secure execution environment comprises the first set of secure execution enclaves and the first set of secure datapaths.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: September 3, 2024
    Assignee: Intel Corporation
    Inventors: Kapil Sood, Ioannis T. Schoinas, Yu-Yuan Chen, Raghunandan Makaram, David J. Harriman, Baiju Patel, Ronald Perez, Matthew E. Hoekstra, Reshma Lal
  • Patent number: 12080563
    Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Chen, Yu-Min Liang, Yen-Ping Wang, Jiun Yi Wu, Chen-Hua Yu, Kai-Chiang Wu
  • Patent number: 12080688
    Abstract: A light-emitting diode (LED) packaging module includes LED chips, a wiring layer, and an encapsulant component. Each of the LED chips includes a chip first surface, a chip second surface, a chip side surface, and an electrode unit. The wiring layer is disposed on the chip second surfaces of the LED chips, and contacts and is electrically connected to the electrode units. The encapsulant component includes a first encapsulating layer that covers the chip side surface, and a second encapsulating layer that covers the wiring layer. The LED chip has a thickness TA, the first encapsulating layer has a thickness TB, in which TB/TA?1.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: September 3, 2024
    Assignee: Quanzhou Sanan Semiconductor Technoogy Co., Ltd.
    Inventors: Zhen-Duan Lin, Yanqiu Liao, Shuning Xin, Weng-Tack Wong, Junpeng Shi, Aihua Cao, Changchin Yu, Chi-Wei Liao, Chen-ke Hsu, Zheng Wu, Chia-en Lee
  • Patent number: 12080952
    Abstract: An antenna module is disposed to an electronic device includes a fixed member, a rotating component, a reflector, a director, and an antenna unit. The electronic device includes a first body and a second body. The first body has a first surface and a second surface. The fixed member is disposed to the first body fixedly. The rotating component is connected to the fixed member rotatably. The reflector and the director are disposed to the rotating component. The antenna unit is disposed to the first body and between the reflector and the director. When the first body and the second body rotate relative to each other, the reflector is located between the antenna unit and one of the first surface and the second surface, and the director is located between the antenna unit and another one of the first surface and the second surface.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: September 3, 2024
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Jo-Fan Chang, Yu Chen, Jhih-Ning Cheng, Yu-Hsun Huang
  • Patent number: 12080036
    Abstract: An image processing method including the following steps is provided. An image information of an image is received, wherein the image includes a plurality of blocks and the image information includes a plurality of pixel information of each block. A dual gamma correction is performed on a first group of blocks of the image to obtain one or more corrected blocks and the dual gamma correction is skipped on a second group of blocks of the image to obtain a plurality of uncorrected blocks. A first encoding process is performed on the one or more corrected blocks to obtain a plurality of first encoded blocks. A second encoding process different from the first encoding process is performed on the plurality of uncorrected blocks to obtain a plurality of second encoded blocks.
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: September 3, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventors: Hui-Yu Jiang, Heng-Yao Lin, Yen-Tao Liao
  • Patent number: 12081177
    Abstract: A full-bridge class-D amplifier circuit comprises first through fourth power devices. First conduction terminals of the first and third power devices are coupled to a first power supply voltage, and second conduction terminals of the second and fourth power devices are coupled to a second power supply voltage. A second conduction terminal of the first power device and a first conduction terminal of the second power device are coupled to a first amplifier output. A second conduction terminal of the third power device and a first conduction terminal of the fourth power device are coupled to a second amplifier output. Left and right driver devices respectively disposed adjacent to left and right sides of the first power device have outputs respectively coupled to left and right control terminals respectively disposed on the left and right sides of the first power device.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: September 3, 2024
    Assignees: Analog Power Conversion LLC, Kyosan Electric Manufacturing Co., Ltd.
    Inventors: Sam Seiichiro Ochi, Dumitru Gheorge Sdrulla, W. Albert Gu, Tetsuya Takata, Itsuo Yuzurihara, Tomohiro Yoneyama, Yu Hosoyamada
  • Patent number: 12077790
    Abstract: The invention provides for optimized binuclease fusion proteins with increased pharmacokinetic properties. The optimized binuclease fusion proteins of the invention two or more nuclease domains (e.g., RNase and DNase domain) operably coupled to an Fc domain. The invention also provides methods of treating or preventing a condition associated with an abnormal immune response.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: September 3, 2024
    Assignee: Resolve Therapeutics, LLC
    Inventors: James Arthur Posada, Sanjay Patel, Weihong Yu, Chris Gabel
  • Patent number: 12080482
    Abstract: A ceramic electronic device includes: a multilayer chip in which each of dielectric layers and each of internal electrode layers are alternately stacked, a main component of the dielectric layers being BaTiO3, wherein a rare earth element that is at least one of Gd, Tb, Dy, Ho, Y and Er is solid-solved in both of an A site and a B site of BaTiO3 of the dielectric layers.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 3, 2024
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Yu Sugawara
  • Patent number: 12082509
    Abstract: A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2/capping layer configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance x area (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable net magnetoresistive ratio (DRR). Moreover, magnetizations in first and second pinned layers, PL1 and PL2, respectively, are aligned antiparallel to enable a lower critical switching current than when in a parallel alignment. An oxide capping layer having a RACAP is formed on PL2 to provide higher PL2 stability. The condition RA1<RA2 and RACAP<RA2 is achieved when TB1 and the oxide capping layer have one or both of a smaller thickness and a lower oxidation state than TB2, are comprised of conductive (metal) channels in a metal oxide or metal oxynitride matrix, or are comprised of a doped metal oxide or doped metal oxynitride layer.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Vignesh Sundar, Yu-Jen Wang, Luc Thomas, Guenole Jan, Sahil Patel, Ru-Ying Tong
  • Patent number: 12080794
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: September 3, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yu Yang, Shin-Hung Li, Nien-Chung Li, Chang-Po Hsiung
  • Patent number: 12082193
    Abstract: Apparatuses, methods, and systems are disclosed for sidelink control information indication. One apparatus includes a receiver that receives a second control information message from a remote unit over sidelink communication. Here, the second control information is in response to the remote unit receiving one or more data processes scheduled by a first control information message from a relay unit. The apparatus also includes a processor that determines a transmission-reception pattern for the sidelink communication and generates an indicator of the determined transmission-reception pattern. The apparatus further includes a transmitter that transmits the indicator of the determined transmission-reception pattern to the remote unit in a third control information message.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: September 3, 2024
    Assignee: Motorola Mobility LLC
    Inventors: Xiaodong Yu, Haipeng Lei, Chenxi Zhu, Zhi Yan, Hongchao Li
  • Patent number: D1040622
    Type: Grant
    Filed: February 20, 2024
    Date of Patent: September 3, 2024
    Assignee: Shenzhen Tuanxin Intelligent Technology Co., Ltd.
    Inventor: Yindi Yu
  • Patent number: D1040630
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: September 3, 2024
    Assignee: MAKITA CORPORATION
    Inventors: Kazunori Hattori, Yu Eto
  • Patent number: D1040746
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: September 3, 2024
    Assignee: CHARGEPOINT, INC.
    Inventors: Justin D. Cumming, William Rich, Stan C. Reyes, Benjamin Bylenok, Kevin Fetterman, Jacob Heth, Jeffrey Barone, John Hsudan Yu, Pasquale Romano, Stephen Eric Sidle, Aaron Dayton Little