Abstract: An interconnect structure, along with methods of forming such, are described. In some embodiments, the method includes forming a first dielectric layer over one or more devices, forming a first conductive feature in the first dielectric layer, and forming two dielectric features over the first dielectric layer and the first conductive feature. At least one of the two dielectric features has a first width, and each dielectric feature includes a first low-k dielectric layer, an oxide layer, and a first etch stop layer. The method further includes forming a second conductive feature between the two dielectric features, and the second conductive feature has a second width substantially the same as the first width.

Abstract: A saddle includes a main body, a protecting layer, a sensing module, a base cover and a bow element. An inside of the main body defines an accommodating space. A rear end of the bottom surface of the main body is recessed inward to form a notch. The protecting layer is attached to a top of the main body. The sensing module is disposed in the accommodating space through the notch. The sensing module includes a circuit board and a barometric pressure sensor. The barometric pressure sensor is disposed on a top surface of the circuit board. The barometric pressure sensor and the main body are separated by the accommodating space. The base cover is disposed to the bottom surface of the main body. Atop surface of the base cover extends upward to form a fastening pillar. The fastening pillar is inserted into the accommodating space.

Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.

Abstract: An over-current protection device includes first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer includes a polymer matrix, a conductive filler, and a titanium-containing dielectric filler. The polymer matrix has a fluoropolymer. The titanium-containing dielectric filler has a compound represented by a general formula of MTiO3, wherein the M represents transition metal or alkaline earth metal. The total volume of the PTC material layer is calculated as 100%, and the titanium-containing dielectric filler accounts to for 5-15% by volume of the PTC material layer.

Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.

Abstract: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a first gate structure on the substrate and adjacent to the STI, forming a first doped region between the first gate structure and the STI, forming a second doped region between the first doped region and the first gate structure, forming a first contact plug on the first doped region, and then forming a second contact plug on the second doped region.

Abstract: The present disclosure provides a radar object recognition method, which includes steps as follows. The radar image generation is performed on radar data to generate a radar image; the radar image is inputted into an object recognition model, so that the object recognition model outputs a recognition result; the post-process is performed on the recognition result to eliminate recognition errors from the recognition result.

Abstract: The present disclosure relates to a method for treating a cancer and/or cancer metastasis in a subject comprising administering to the subject irinotecan loaded in a mesoporous silica nanoparticle. The present disclosure also provides a conjugate comprising an agent loaded in a mesoporous silica nanoparticle (MSN) defining at least one pore and having at least one functional group on a sidewall of the at least one pore.

Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a polymer matrix and a first conductive filler. The polymer matrix includes a polyolefin-based polymer and a fluoropolymer. The fluoropolymer has a melt flow index higher than 1.9 g/10 min, and the polyolefin-based polymer and the fluoropolymer together form an interpenetrating polymer network (IPN). The first conductive filler has a metal-ceramic compound dispersed in the polymer matrix.

Abstract: An electronic includes an electronic element, an encapsulation layer surrounding the electronic element, a first circuit structure, a second circuit structure and a connecting structure. The encapsulation layer has a top surface, a bottom surface and an opening, wherein a sidewall of the opening connects the top surface and the bottom surface. The first circuit structure is disposed at the top surface of the encapsulation layer. The second circuit structure is disposed at the bottom surface of the encapsulation layer. The connecting structure is disposed in the opening, wherein the electronic element is electrically connected to the second circuit structure through the first circuit structure and the connecting structure. The connecting structure includes a first sub layer and a second sub layer, the first sub layer is located between the encapsulation layer and the second sub layer, and the first sub layer covers the sidewall of the opening.

Abstract: An over-current protection device includes first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer includes a polymer matrix, and a conductive filler. The polymer matrix has a fluoropolymer. The total volume of the PTC material layer is calculated as 100%, and the fluoropolymer accounts for 47-62% by volume of the PTC material layer. The fluoropolymer has a melt viscosity higher than 3000 Pa·s.

Abstract: A display device includes a first display unit emitting a green light having a first output spectrum corresponding to a highest gray level of the display device and a second display unit emitting a blue light having a second output spectrum corresponding to the highest gray level of the display device. The first output spectrum has a main wave with a first peak. The second output spectrum has a main wave with a second peak and a sub wave with a sub peak. The second peak corresponds to a main wavelength, the sub peak corresponds to a sub wavelength, and the main wavelength is less than the sub wavelength. An intensity of the second peak is greater than an intensity of the sub peak and an intensity of the first peak.

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a first mesa isolation on the HEMT region and a second mesa isolation on the capacitor region, forming a HEMT on the first mesa isolation, and then forming a capacitor on the second mesa isolation.

Abstract: A guided cold-atom inertial sensor system comprises an atom trap integrated platform, a laser system, a magnetic field system, a control system, and a computing system. The laser system and magnetic field system are adapted to form a magneto-optical trap (MOT) about a suspended waveguide of the atom trap integrated platform made of membrane integrated photonics. After loading cold atoms from a MOT, the photonic atom trap integrated platform generates one-dimensional guided atoms with an evanescent field optical dipole trap (EF-ODT) along the optical waveguide to create guided atomic accelerometers/gyroscopes. Motion of atomic wavepackets in a superposition state is created along the guided atom geometry by way of state-dependent momentum kicks. The light-pulse sequence of guided atom interferometry splits, redirects, and recombines atomic wavepackets, which allows measurement of atom interference fringes sensitive to inertial forces via a probe laser.

Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure over a substrate. A data storage structure overlies the first conductive structure. The data storage structure comprises a first dielectric layer on the first conductive structure and a second dielectric layer on the first dielectric layer. The first dielectric layer comprises a dielectric material and a first dopant having a concentration that changes from a top surface of the first dielectric layer in a direction towards the first conductive structure. A second conductive structure overlies the data storage structure.

Abstract: A display device includes a substrate, at least one light emitting unit bound on the substrate, a transparency controllable unit disposed on the substrate, and an integrated circuit unit overlapped with the substrate. The integrated circuit unit includes a semiconducting structure and a conductive structure overlapped with the semiconducting structure. The integrated circuit unit is electrically connected to the at least one light emitting unit and the transparency controllable unit.

Abstract: An electronic device includes a substrate, a semiconductor unit and an insulating layer. The semiconductor unit is disposed on the substrate. The insulating layer is disposed on the semiconductor unit, and the insulating layer includes a first portion and a second portion connected to the first portion. In a top view, the first portion partially overlaps the semiconductor unit, the second portion does not overlap the semiconductor unit, and a part of an edge of the insulating layer is irregular.

Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.