Patents by Inventor An Zhu
An Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230063535Abstract: Provided are a depth image processing method, and a small obstacle detection method and system. The method comprises calibration of sensors, distortion and epipolar rectification, data alignment, and sparse stereo matching. The depth image processing method and the small obstacle detection method and system of the present invention only requires execution of sparse stereo matching on hole portions of a structured light depth image, and do not requires stereo matching of the entire image, thereby significantly reducing the overall computation load for processing a depth image, and enhancing the robustness of a system.Type: ApplicationFiled: December 9, 2020Publication date: March 2, 2023Inventors: Yong LIU, Jun An ZHU, Yin HUANG, Cong GUO
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Patent number: 11404209Abstract: An electrical device package structure and manufacturing method thereof is disclosed. The manufacturing method comprises: providing an electrical device body having at least two electrodes, wherein an outer surface of the electrical device body is partially covered by the electrodes, and outer surfaces of the electrodes are covered by a plastic material; forming a first protective layer including phosphate salt at least on the exposed outer surface of the electrical device body; and forming a second protective layer including glass at least on an exposed outer surface of the first protective layer. The present invention can prevent the electrical device body and/or the electrodes from being damaged on their manufacturing process, and avoid a forming high impedance layer on an electrode.Type: GrantFiled: July 10, 2020Date of Patent: August 2, 2022Assignee: SFI Electronics Technology Inc.Inventors: Ching-Hohn Len, Hong Zong Xu, Zhi Xian Xu, Hsing Tsai Huang, Jie-An Zhu
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Publication number: 20210280373Abstract: An electrical device package structure and manufacturing method thereof is disclosed. The manufacturing method comprises: providing an electrical device body having at least two electrodes, wherein an outer surface of the electrical device body is partially covered by the electrodes, and outer surfaces of the electrodes are covered by a plastic material; forming a first protective layer including phosphate salt at least on the exposed outer surface of the electrical device body; and forming a second protective layer including glass at least on an exposed outer surface of the first protective layer. The present invention can prevent the electrical device body and/or the electrodes from being damaged on their manufacturing process, and avoid a forming high impedance layer on an electrode.Type: ApplicationFiled: July 10, 2020Publication date: September 9, 2021Inventors: Ching-Hohn Len, Hong Zong Xu, Zhi Xian Xu, Hsing Tsai Huang, Jie-An Zhu
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Publication number: 20190255564Abstract: A liquid-repellent surface is provided where the repellency arises solely from the re-entrant surface structure. The liquid repellent surface is a porous membrane that contains hexagonally packed microcavities, each of which has a narrow opening located on its top. The surface is mechanically robust because the microstructures are interconnected in a continuous manner. A method of preparing the liquid repellent surface is also provided, which involves producing a uniform emulsion containing monodisperse micro-droplets, depositing the emulsion onto a substrate, and solidifying the emulsion-deposit by evaporating the solvent in the continuous phase fluid.Type: ApplicationFiled: November 4, 2016Publication date: August 22, 2019Inventors: Liqiu WANG, Ping An ZHU
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Patent number: 10057350Abstract: A method, non-transitory computer readable medium, and device that assists with transferring data based on actual size of a data operation includes receiving a data operation from a client computing device. A type of the received data operation is determined and additional memory size associated with the determined type of the received data operation is identified. Next, a non-volatile log file is updated with the identified additional memory size and the determined type of the received data operation.Type: GrantFiled: December 28, 2015Date of Patent: August 21, 2018Assignee: NetApp, Inc.Inventors: Travis Callahan, An Zhu, Sandeep Budanur, Mrinal Bhattacharjee
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Patent number: 9947444Abstract: A process for producing a multilayer varistor (MLV) if remained its size unchanged as prior arts is favorable to outstandingly increase overall current-carrying area and improve the performance of final produced MLV; and the MLV has laminated a lower cap, an inner-electrode stack formed from piling up several inner-electrode gaps (g), and an upper cap into a unity, and at least satisfies the condition that the lower cap and the upper cap has a thickness smaller than a thickness of the inner-electrode gap (g), but equal to or greater than 0.1 times of the thickness of the inner-electrode gap (g).Type: GrantFiled: September 20, 2017Date of Patent: April 17, 2018Assignee: SFI ELECTRONICS TECHNOLOGY INC.Inventors: Ching-Hohn Lien, Jie-An Zhu, Zhi-Xian Xu, Ting-Yi Fang, Hong-Zong Xu
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Publication number: 20180090248Abstract: A process for producing a multilayer varistor (MLV) if remained its size unchanged as prior arts is favorable to outstandingly increase overall current-carrying area and improve the performance of final produced MLV; and the MLV has laminated a lower cap, an inner-electrode stack formed from piling up several inner-electrode gaps (g), and an upper cap into a unity, and at least satisfies the condition that the lower cap and the upper cap has a thickness smaller than a thickness of the inner-electrode gap (g), but equal to or greater than 0.1 times of the thickness of the inner-electrode gap (g).Type: ApplicationFiled: September 20, 2017Publication date: March 29, 2018Inventors: Ching-Hohn LIEN, Jie-An ZHU, Zhi-Xian XU, Ting-Yi FANG, Hong-Zong XU
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Publication number: 20170187804Abstract: A method, non-transitory computer readable medium, and device that assists with transferring data based on actual size of a data operation includes receiving a data operation from a client computing device. A type of the received data operation is determined and additional memory size associated with the determined type of the received data operation is identified. Next, a non-volatile log file is updated with the identified additional memory size and the determined type of the received data operation.Type: ApplicationFiled: December 28, 2015Publication date: June 29, 2017Inventors: Travis Callahan, An Zhu, Sandeep Budanur, Mrinal Bhattacharjee
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Patent number: 9443825Abstract: A surface-mount device (SMD) uses no conventional lead frame and contains a multi-function die module formed from either a single die or two or more dies electrically connected in series, in parallel, or in any combination of series and parallel, to provide such a SMD having one or more different functions including wave filtration, rectification, surge protection, sensing, current limiting, voltage regulation or prevention from voltage backflow, as compared to the prior art, the SMD disclosed is formed from fewer components, is simpler to manufacture and more effectively reduce layout wire length and noise.Type: GrantFiled: February 9, 2016Date of Patent: September 13, 2016Assignee: SFI ELECTRONICS TECHNOLOGY INC.Inventors: Ching-Hohn Lien, Xing-Xiang Huang, Hsing-Tsai Huang, Jie-An Zhu, Hong-Zong Xu, Yi-Wei Chen, Jung-Chun Chiang
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Publication number: 20160240510Abstract: A surface-mount device (SMD) uses no conventional lead frame and contains a multi-function die module formed from either a single die or two or more dies electrically connected in series, in parallel, or in any combination of series and parallel, to provide such a SMD having one or more different functions including wave filtration, rectification, surge protection, sensing, current limiting, voltage regulation or prevention from voltage backflow, as compared to the prior art, the SMD disclosed is formed from fewer components, is simpler to manufacture and more effectively reduce layout wire length and noise.Type: ApplicationFiled: February 9, 2016Publication date: August 18, 2016Inventors: Ching-Hohn LIEN, Xing-Xiang HUANG, Hsing-Tsai HUANG, Jie-An ZHU, Hong-Zong XU, Yi-Wei CHEN, Jung-Chun CHIANG
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Publication number: 20160124786Abstract: A method, non-transitory computer readable medium, and device that identifies race condition at run time includes monitoring a client device processor during execution of an operation by the client device processor. An interrupt in the monitored client device processor is identified and a delay is introduced in the monitored client device processor during the execution of the monitored client device processor upon identifying the interrupt. A race condition in a completed operation is determined using information associated with the introduced delay. Information associated with the race condition is recorded when the completed operation is determined to have resulted in the race condition.Type: ApplicationFiled: November 4, 2014Publication date: May 5, 2016Inventor: An Zhu
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Patent number: 8488291Abstract: A ZnO surge arrester for high-temperature operation is characterized in that a grain boundary layer between ZnO grains thereof contains a BaTiO3-based positive temperature coefficient thermistor material, which takes 10-85 mol % in the overall grain boundary layer, and when operating temperature raises, the positive temperature coefficient thermistor material in the grain boundary layer has its resistance sharply increasing with the raising temperature, so as to compensate or partially compensate decrease in resistance of components in the grain boundary layer caused by the raising temperature, thereby making the resistance of the grain boundary layer in the ZnO surge arrester more independent of temperature. The ZnO surge arrester thus is suitable for operation where a maximum operating temperature is higher than 125° C., or even higher than 150° C.Type: GrantFiled: February 9, 2011Date of Patent: July 16, 2013Assignee: SFI Electronics Technology Inc.Inventors: Ching-Hohn Lien, Jie-An Zhu, Zhi-Xian Xu, Xing-Xiang Huang, Ting-Yi Fang
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Publication number: 20130133183Abstract: A process for producing zinc oxide varistor is disclosed to allow that one step of having zinc oxide grains doped with non-equivalent ions and sufficiently semiconductorized and the other one step of preparing sintered powders having property of high-impedance are prepared by two separate procedures respectively, resulted in that the zinc oxide varistor produced by the process features both a high potential gradient and a high non-linearity coefficient; and more particularly the disclosed process is suited for producing a specific zinc oxide varistor whose potential gradient ranges from 2,000 to 9000 V/mm as well as non-linearity coefficient (?) ranges from 21.5 to 55.Type: ApplicationFiled: September 11, 2012Publication date: May 30, 2013Inventors: Ching-Hohn LIEN, Jie-An ZHU
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Publication number: 20130011963Abstract: A process for producing zinc oxide varistors possessed a property of breakdown voltage (V1mA) ranging from 230 to 1,730 V/mm is to perform the doping of zinc oxide and the sintering of zinc oxide grains with a high-impedance sintered powder through two independent procedures, so that the doped zinc oxide and the high-impedance sintered powder are well mixed in a predetermined ratio and then used to make the zinc oxide varistors through conventional technology by low-temperature sintering (lower than 900° C.); the resultant zinc oxide varistors may use pure silver as inner electrode and particularly possess breakdown voltage ranging from 230 to 1,730 V/mm.Type: ApplicationFiled: September 13, 2012Publication date: January 10, 2013Applicant: SFI ELECTRONICS TECHNOLOGY INC.Inventors: Ching-Hohn LIEN, Jie-An ZHU, Zhi-Xian XU, Hong-Zong XU, Ting-Yi FANG, Xing-Xiang HUANG
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Patent number: 8313672Abstract: A kind of manufacturing method for dual functions with varistor material and device has one of the characteristics among capacitance, inductance, voltage suppressor and thermistor in addition to surge absorbing characteristic, which microstructural compositions include a glass substrate with high resistance and three kinds of low-resistance conductive or semiconductive particles in micron, submicron and nanometer size uniformly distributed in the glass substrate to provide with good surge absorbing characteristic.Type: GrantFiled: September 3, 2009Date of Patent: November 20, 2012Assignee: Leader Well Technology Co., Ltd.Inventors: Yu-Wen Tan, Jie-An Zhu, Li-Yun Zhang
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Patent number: 8263432Abstract: A material composition having a core-shell microstructure suitable for manufacturing a varistor having outstanding electrical properties, the core-shell microstructure of the material composition at least comprising a cored-structure made of a conductive or semi-conductive material and a shelled-structure made from a glass material to wrap the cored-structure, and electrical properties of the varistors during low temperature of sintering process can be decided and designated by precisely controlling the size of the grain of the cored-structure and the thickness and insulation resistance of the insulating layer of the shelled-structure of material composition.Type: GrantFiled: May 17, 2007Date of Patent: September 11, 2012Assignee: Bee Fund Biotechnology Inc.Inventors: Ching-Hohn Lien, Cheng-Tsung Kuo, Jun-Nan Lin, Jie-An Zhu, Li-Yun Zhang, Wei-Cheng Lien
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Publication number: 20120135563Abstract: A low-temperature firing process is available for cost saving to produce a multilayer chip ZnO varistor containing pure silver (Ag) formed as internal electrodes and calcined at ultralow firing temperature of 850-900° C., which process comprises: a) individually preparing ZnO grains in advance doped with doping ions for promotion of semi-conductivity of ZnO grains if calcined; b) individually preparing a desired high-impedance sintering material to be fired as grain boundaries to encapsulate ZnO grains; c) mixing the doped ZnO grains of Step a) with the high-impedance sintering material of Step b) in a predetermined ratio to form a mixture and proceeding with an initial sintering to have the mixture sintered and ground as composite ZnO ceramic powders, and d) processing the sintered mixture of Step c) to make multilayer chip ZnO varistors containing pure silver (Ag) internal electrodes but sintered at ultralow firing temperature of 850-900° C.Type: ApplicationFiled: November 17, 2011Publication date: May 31, 2012Applicant: SFI Electronics Technology Inc.Inventors: Ching-Hohn LIEN, Jie-An ZHU
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Publication number: 20120057265Abstract: A ZnO surge arrester for high-temperature operation is characterized in that a grain boundary layer between ZnO grains thereof contains a BaTiO3-based positive temperature coefficient thermistor material, which takes 10-85 mol % in the overall grain boundary layer, and when operating temperature raises, the positive temperature coefficient thermistor material in the grain boundary layer has its resistance sharply increasing with the raising temperature, so as to compensate or partially compensate decrease in resistance of components in the grain boundary layer caused by the raising temperature, thereby making the resistance of the grain boundary layer in the ZnO surge arrester more independent of temperature. The ZnO surge arrester thus is suitable for operation where a maximum operating temperature is higher than 125° C., or even higher than 150° C.Type: ApplicationFiled: February 9, 2011Publication date: March 8, 2012Applicant: SFI Electronics Technology Inc.Inventors: Ching-Hohn LIEN, Jie-An Zhu, Zhi-Xian Xu, Xing-Xiang Huang, Ting-Yi Fang
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Patent number: 7962564Abstract: A computer program product, apparatus and method for identifying processors in a multi-tasking multiprocessor network, the computer program product including a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method including storing a service record for a port to which an LID has been assigned, retrieving service records for nodes to which channel paths may connect, retrieving path records that provide address destinations for the nodes identified in the service records, initiating channel initialization for the channel paths defined for the port and removing the service record for the port.Type: GrantFiled: February 25, 2008Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Richard K. Errickson, Welela Haileselaissie, Leornard W. Helmer, Jr., John S. Houston, An Zhu
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Patent number: D848654Type: GrantFiled: August 21, 2017Date of Patent: May 14, 2019Assignee: OPPLE LIGHTING CO., LTD.Inventor: An Zhu