Abstract: An N+1 frequency divider counter (20) has a binary counter (22), ones detect circuitry (26), control logic (24), and an output flip-flop (28). The binary counter (22) counts from an initial value to a final value for each half of an output clock signal. If N+1 is an even number, one full cycle is added to each half cycle of the output clock signal. If N+1 is an odd number, one-half of a cycle is added to each half phase of the output clock signal. At the final count value, the control logic (24) causes the output clock signal to transition on either the rising edge or the falling edge of an input clock signal. The N+1 counter (20) has a fifty percent duty cycle for all count values of N, and does not require additional circuitry to accommodate when N equals zero.

Abstract: A lock detection circuit (112) includes a first sampler (113) which samples an input signal (102) at a rate of an output signal (109) to provide a sampled input signal. A second sampler (114) which samples a feedback signal (111) at the rate of the output signal (109) to provide a sampled feedback signal. The sampled input signal is subsequently sampled by a third sampler (115) at the rate of the feedback signal. The sampled feedback signal is subsequently sampled by a fourth sampler (116) at the rate of the input signal. The second sampled input signal and the second sampled feedback signal are subsequently compared (117) and when they substantially match, an indication (122) is set to indicate that phase and/or frequency lock has been obtained.

Abstract: A combined multiplier/shifter (150) uses an existing high-speed multiplier to perform both multiplies and programmable left and right shifts without a dedicated high-speed shifter. A shift decoder (160) used in a shift mode provides first recoded signals according to a shift count and a shift direction. A recoder (161) recodes a multiplier input in a multiply mode to provide second recoded signals. A multiplier array (163) receives either a multiplicand or a shift operand at its multiplicand input, and uses either the first or second recoded signals selectively according to the mode. An output of the multiplier array (163) is either a product in the multiply mode or a first shift result in the shift mode. An output shifter (157) selectively adjusts the first shift result according to the shift direction to provide a second, final shift result.