Patents by Inventor Anabela Veloso
Anabela Veloso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230142597Abstract: A method of producing an IC chip is provided. In one aspect, deep trenches are formed in a semiconductor layer that forms the top layer of a device wafer, the trenches going through the complete thickness of the layer. The trenches are filled with a sacrificial material, that is etched back and covered with a capping layer, thereby forming sacrificial buried rails. After processing active devices on the front surface of the semiconductor layer, including connections to the sacrificial rails, the device wafer is bonded face down to a carrier wafer, and thinned from the back side, until the sacrificial rails are exposed. The sacrificial material and the capping layer are removed and replaced by a conductive material, thereby forming the actual buried power rails. A back side power delivery network supplies power through the buried rails to the active devices of the IC. Using a sacrificial material for the buried rails can enable a wider choice of materials for these buried rails.Type: ApplicationFiled: October 19, 2022Publication date: May 11, 2023Inventors: Anabela Veloso, Eric Beyne, Anne Jourdain
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Publication number: 20230080522Abstract: An integrated circuit (IC) chip is provided. In one aspect, a semiconductor substrate includes active devices on its front surface and power delivery tracks on its back surface. The active devices are powered through mutually parallel buried power rails, with the power delivery tracks running transversely with respect to the power rails, and connected to the power rails by a plurality of Through Semiconductor Via connections, which run from the power rails to the back of the substrate. The TSVs are elongate slit-shaped TSVs aligned to the power rails and arranged in a staggered pattern, so that any one of the power delivery tracks is connected to a first row of mutually parallel TSVs, and any power delivery track directly adjacent to the power delivery track is connected to another row of TSVs which are staggered relative to the TSVs of the first row. A method of producing an IC chip includes producing the slit-shaped TSVs before the buried power rails.Type: ApplicationFiled: September 15, 2022Publication date: March 16, 2023Inventors: Eric Beyne, Anne Jourdain, Anabela Veloso
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Patent number: 11217488Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having vertical channel field-effect transistor (FET) devices comprises forming on a substrate, a plurality of semiconductor structures protruding vertically from a lower source/drain semiconductor layer of the substrate. The semiconductor structures can be arranged in an array having a plurality of rows and columns. The method can include etching metal line trenches between at least a subset of the rows and forming metal lines in the metal line trenches to contact the lower source/drain layer. The method can also include forming gate structures at least partly enclosing semiconductor structure channel portions located above the lower source/drain layer and forming upper source/drain metal contacts on semiconductor structure upper source/drain portions located above the channel portions.Type: GrantFiled: March 31, 2020Date of Patent: January 4, 2022Assignee: IMEC zvwInventors: Anabela Veloso, Trong Huynh Bao, Raf Appeltans
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Patent number: 11201093Abstract: A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.Type: GrantFiled: March 31, 2020Date of Patent: December 14, 2021Assignee: IMEC vzwInventors: Anabela Veloso, Trong Huynh Bao, Julien Ryckaert, Raf Appeltans
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Publication number: 20210336057Abstract: A semiconductor structure comprises a semiconductor substrate having a top layer and one or more semiconductor monocrystalline nanostructures. Each nanostructure has a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a distance, and a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The source and drain structures are made of a p-doped (or alternatively n-doped) semiconductor monocrystalline material having a smaller (or alternatively larger) unstrained lattice constant than the unstrained lattice constant of the semiconductor monocrystalline material making the semiconductor monocrystalline nanostructure on which they are grown, thereby creating compressive (or alternatively tensile) strain in that semiconductor monocrystalline nanostructure.Type: ApplicationFiled: April 27, 2021Publication date: October 28, 2021Inventors: Geert Eneman, Basoene Briggs, An De Keersgieter, Anabela Veloso, Paola Favia
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Patent number: 11088263Abstract: The disclosed technology relates generally to semiconductor processing and more particularly to a method of forming a vertical field-effect transistor device. According to an aspect, a method of forming a vertical field-effect transistor device comprises forming on a substrate a vertical semiconductor structure protruding above the substrate and comprising a lower source/drain portion, an upper source/drain portion and a channel portion arranged between the lower source/drain portion and the upper source/drain portion.Type: GrantFiled: June 4, 2020Date of Patent: August 10, 2021Assignee: IMEC vzwInventors: Anabela Veloso, Geert Eneman
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Patent number: 11018235Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.Type: GrantFiled: November 11, 2016Date of Patent: May 25, 2021Assignees: IMEC vzw, Vrije Universiteit BrusselInventors: Trong Huynh Bao, Anabela Veloso, Julien Ryckaert
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Patent number: 10957793Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of forming a target layer surrounding a vertical nanostructure. In one aspect, a method includes providing a substrate having a substrate surface. The method additionally includes forming a vertical nanostructure extending outwardly from a substrate surface. The vertical nanostructure has a sidewall surface, where the sidewall surface has an upper portion and a lower portion. The method additionally includes forming a target layer at least along the sidewall surface of the vertical nanostructure and on the substrate surface. The method additionally includes forming a protection layer covering the target layer and removing an upper portion of the protection layer, thereby exposing the target layer along the upper portion of the sidewall surface of the vertical nanostructure.Type: GrantFiled: September 11, 2018Date of Patent: March 23, 2021Assignee: IMEC vzwInventors: Vasile Paraschiv, Guglielma Vecchio, Anabela Veloso
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Publication number: 20200388698Abstract: The disclosed technology relates generally to semiconductor processing and more particularly to a method of forming a vertical field-effect transistor device. According to an aspect, a method of forming a vertical field-effect transistor device comprises forming on a substrate a vertical semiconductor structure protruding above the substrate and comprising a lower source/drain portion, an upper source/drain portion and a channel portion arranged between the lower source/drain portion and the upper source/drain portion.Type: ApplicationFiled: June 4, 2020Publication date: December 10, 2020Inventors: Anabela Veloso, Geert Eneman
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Publication number: 20200312721Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having vertical channel field-effect transistor (FET) devices comprises forming on a substrate, a plurality of semiconductor structures protruding vertically from a lower source/drain semiconductor layer of the substrate. The semiconductor structures can be arranged in an array having a plurality of rows and columns. The method can include etching metal line trenches between at least a subset of the rows and forming metal lines in the metal line trenches to contact the lower source/drain layer. The method can also include forming gate structures at least partly enclosing semiconductor structure channel portions located above the lower source/drain layer and forming upper source/drain metal contacts on semiconductor structure upper source/drain portions located above the channel portions.Type: ApplicationFiled: March 31, 2020Publication date: October 1, 2020Inventors: Anabela VELOSO, Trong HUYNH BAO, Raf APPELTANS
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Publication number: 20200312725Abstract: The disclosed technology relates to methods of fabricating field-effect transistors having channels extending in horizontal and vertical directions.Type: ApplicationFiled: March 31, 2020Publication date: October 1, 2020Inventors: Anabela Veloso, Trong Huynh Bao, Julien Ryckaert, Raf Appeltans
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Publication number: 20200312726Abstract: A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.Type: ApplicationFiled: March 31, 2020Publication date: October 1, 2020Inventors: Anabela Veloso, Trong Huynh Bao, Julien Ryckaert, Raf Appeltans
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Publication number: 20190198643Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a vertical channel device and a method of fabricating the same. According to one aspect, a method for fabricating a vertical channel device includes forming a vertical semiconductor structure including an upper portion, an intermediate portion and a lower portion, by etching a semiconductor layer stack arranged on a substrate. The semiconductor layer stack includes an upper semiconductor layer, an intermediate semiconductor layer and a lower semiconductor layer, wherein the intermediate semiconductor layer is formed of a material different from a material of the lower semiconductor layer and different from a material of the upper semiconductor layer.Type: ApplicationFiled: December 14, 2018Publication date: June 27, 2019Inventors: Boon Teik Chan, Anabela Veloso, Efrain Altamirano Sanchez, Zheng Tao
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Publication number: 20190097047Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of forming a target layer surrounding a vertical nanostructure. In one aspect, a method includes providing a substrate having a substrate surface. The method additionally includes forming a vertical nanostructure extending outwardly from a substrate surface. The vertical nanostructure has a sidewall surface, where the sidewall surface has an upper portion and a lower portion. The method additionally includes forming a target layer at least along the sidewall surface of the vertical nanostructure and on the substrate surface. The method additionally includes forming a protection layer covering the target layer and removing an upper portion of the protection layer, thereby exposing the target layer along the upper portion of the sidewall surface of the vertical nanostructure.Type: ApplicationFiled: September 11, 2018Publication date: March 28, 2019Inventors: Vasile Paraschiv, Guglielma Vecchio, Anabela Veloso
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Publication number: 20190081156Abstract: A device and method for forming a vertical channel device is disclosed.Type: ApplicationFiled: August 31, 2018Publication date: March 14, 2019Applicant: IMEC VZWInventors: Anabela Veloso, Geert Eneman, Nadine Collaert, Erik Rosseel
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Patent number: 9972622Abstract: A method for manufacturing a CMOS device includes providing a semiconductor base layer epitaxially growing a germanium layer on the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed. The method also includes performing an anneal step, thinning the germanium layer and patterning the germanium layer into fin structures or into vertical wire structures. The method further includes laterally embedding the fin structures or vertical wire structures in a dielectric layer and providing a masking layer covering the first region, leaving the second region exposed. The method yet further includes selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench and growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench.Type: GrantFiled: May 12, 2016Date of Patent: May 15, 2018Assignee: IMEC VZWInventors: Liesbeth Witters, Anabela Veloso
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Publication number: 20170358586Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.Type: ApplicationFiled: November 11, 2016Publication date: December 14, 2017Inventors: Trong Huynh Bao, Anabela Veloso, Julien Ryckaert
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Patent number: 9633891Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.Type: GrantFiled: October 28, 2015Date of Patent: April 25, 2017Assignee: IMEC VZWInventors: Nadine Collaert, Geert Eneman, Naoto Horiguchi, Min-Soo Kim, Rita Rooyackers, Anabela Veloso, Liesbeth Witters
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Publication number: 20160336317Abstract: A method for manufacturing a CMOS device includes providing a semiconductor base layer epitaxially growing a germanium layer on the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed. The method also includes performing an anneal step, thinning the germanium layer and patterning the germanium layer into fin structures or into vertical wire structures. The method further includes laterally embedding the fin structures or vertical wire structures in a dielectric layer and providing a masking layer covering the first region, leaving the second region exposed. The method yet further includes selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench and growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench.Type: ApplicationFiled: May 12, 2016Publication date: November 17, 2016Applicant: IMEC VZWInventors: Liesbeth Witters, Anabela Veloso
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Publication number: 20160126131Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.Type: ApplicationFiled: October 28, 2015Publication date: May 5, 2016Applicant: IMEC VZWInventors: Nadine Collaert, Geert Eneman, Naoto Horiguchi, Min-Soo Kim, Rita Rooyackers, Anabela Veloso, Liesbeth Witters