Abstract: Aspects of the disclosure provide a hold violation correction method that can save design time. The method can be integrated into early stages of electric circuit design instead of correcting hold violations during the final stages of circuit design prior to tape-out. The method can include constructing block-level input/output (IO) timing models for a plurality of circuit blocks that are interconnected, detecting one or more paths between the circuit blocks, adding one or more delay elements on the paths to cause that delays on the paths are within a predetermined delay target range.

Abstract: A method and apparatus for synchronizing an asynchronous signal to a clock signal. The apparatus includes an enable generator, first, second and third sampling circuits, a selecting circuit, and can include a latching circuit. The enable generator is coupled to the first sampling circuit by a first enable line, to the second sampling circuit by a second enable line, and to the third sampling circuit by a third enable line. The first, second, and third sampling circuits are coupled to receive the asynchronous signal. The selecting circuit is coupled to receive the output signals of the first, second and third sampling circuits. For the first sampling circuit, the following steps are performed: sampling the asynchronous signal, generating an output signal for the sampling circuit, waiting a period of time, and selecting the sampling circuit's output signal. These steps are also performed for the second sampling circuit and the third sampling circuit.