Patents by Inventor Anand B. Arunagiri

Anand B. Arunagiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10073938
    Abstract: Disclosed aspects relate to verifying an integrated circuit design. A set of design constraints may be received with respect to a verification process for the integrated circuit design. Based on the set of design constraints, a constraint model may be constructed. A new global constraint may be determined using the constraint model. The new global constraint may be used to process the verification process for the integrated circuit design.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Anand B. Arunagiri, Raj K. Gajavelly, Sujeet Kumar, Pradeep K. Nalla
  • Publication number: 20180004879
    Abstract: Disclosed aspects relate to verifying an integrated circuit design. A set of design constraints may be received with respect to a verification process for the integrated circuit design. Based on the set of design constraints, a constraint model may be constructed. A new global constraint may be determined using the constraint model. The new global constraint may be used to process the verification process for the integrated circuit design.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Anand B. Arunagiri, Raj K. Gajavelly, Sujeet Kumar, Pradeep K. Nalla
  • Patent number: 9471327
    Abstract: A tool for formally verifying forwarding paths in an information pipeline. The tool creates two logic design copies of the pipeline to be verified. The tool retrieves a first and a second instruction, which have previously been proven to compute a mathematically correct result when executed separately. The tool defines driver input functions for issuing instructions to the two logic design copies. In accordance with the driver input functions, the tool issues instructions to the two logic design copies. The tool abstracts data flow of the two logic design copies to isolate forwarding paths for verification. The tool adjusts for latency differences between the first and second logic design copies. The tool checks a register for results, and when results from of two logic design copies become available in the register, the tool verifies the results to conclusively prove the correctness of all states of the information pipeline.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anand B. Arunagiri, Udo Krautz, Sujeet Kumar, Viresh Paruthi
  • Patent number: 9459878
    Abstract: A tool for formally verifying forwarding paths in an information pipeline. The tool creates two logic design copies of the pipeline to be verified. The tool retrieves a first and a second instruction, which have previously been proven to compute a mathematically correct result when executed separately. The tool defines driver input functions for issuing instructions to the two logic design copies. In accordance with the driver input functions, the tool issues instructions to the two logic design copies. The tool abstracts data flow of the two logic design copies to isolate forwarding paths for verification. The tool adjusts for latency differences between the first and second logic design copies. The tool checks a register for results, and when results from of two logic design copies become available in the register, the tool verifies the results to conclusively prove the correctness of all states of the information pipeline.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: October 4, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anand B. Arunagiri, Udo Krautz, Sujeet Kumar, Viresh Paruthi
  • Publication number: 20150058601
    Abstract: A tool for formally verifying forwarding paths in an information pipeline. The tool creates two logic design copies of the pipeline to be verified. The tool retrieves a first and a second instruction, which have previously been proven to compute a mathematically correct result when executed separately. The tool defines driver input functions for issuing instructions to the two logic design copies. In accordance with the driver input functions, the tool issues instructions to the two logic design copies. The tool abstracts data flow of the two logic design copies to isolate forwarding paths for verification. The tool adjusts for latency differences between the first and second logic design copies. The tool checks a register for results, and when results from of two logic design copies become available in the register, the tool verifies the results to conclusively prove the correctness of all states of the information pipeline.
    Type: Application
    Filed: August 20, 2013
    Publication date: February 26, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anand B. Arunagiri, Udo Krautz, Sujeet Kumar, Viresh Paruthi
  • Publication number: 20150058604
    Abstract: A tool for formally verifying forwarding paths in an information pipeline. The tool creates two logic design copies of the pipeline to be verified. The tool retrieves a first and a second instruction, which have previously been proven to compute a mathematically correct result when executed separately. The tool defines driver input functions for issuing instructions to the two logic design copies. In accordance with the driver input functions, the tool issues instructions to the two logic design copies. The tool abstracts data flow of the two logic design copies to isolate forwarding paths for verification. The tool adjusts for latency differences between the first and second logic design copies. The tool checks a register for results, and when results from of two logic design copies become available in the register, the tool verifies the results to conclusively prove the correctness of all states of the information pipeline.
    Type: Application
    Filed: January 9, 2014
    Publication date: February 26, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anand B. Arunagiri, UDO KRAUTZ, SUJEET KUMAR, VIRESH PARUTHI