Patents by Inventor Anand Daga

Anand Daga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10013715
    Abstract: Embodiments of the invention are directed to systems, methods and computer program products for use in financial systems, where data communication is automated for purposes of providing temporary waivers. An exemplary apparatus is configured to receive a request from a requesting entity to assign an account a temporary waiver. The account may be associated with one or more services that require a payment for utilizing the service. The system may then send the request to a processing entity to analyzes the request for approval, and receive an approval decision based at least partially on the analysis of the request. In response to receiving the approval decision, the system may process at least one subsequent action for providing or declining a temporary waiver.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: July 3, 2018
    Assignee: Bank of America Corporation
    Inventors: Raghavendran Narasimhan, Gurdeep Singh Walia, Anand Daga, Saroj Kumar Bonthapalli
  • Publication number: 20160019638
    Abstract: Embodiments of the invention are directed to systems, methods and computer program products for use in financial systems, where data communication is automated for purposes of providing temporary waivers. An exemplary apparatus is configured to receive a request from a requesting entity to assign an account a temporary waiver. The account may be associated with one or more services that require a payment for utilizing the service. The system may then send the request to a processing entity to analyzes the request for approval, and receive an approval decision based at least partially on the analysis of the request. In response to receiving the approval decision, the system may process at least one subsequent action for providing or declining a temporary waiver.
    Type: Application
    Filed: July 21, 2014
    Publication date: January 21, 2016
    Inventors: Raghavendran Narasimhan, Gurdeep Singh Walia, Anand Daga, Saroj Kumar Bonthapalli
  • Publication number: 20150188852
    Abstract: A computer system enables a business to support the automation of out-of-office (OOO) messaging when a recipient of e-mail is unavailable. An out-of-office message configurator operates in co-operation with the e-mail application for out-of-service messaging so that configuration information is automatically requested to specify the content of an OOO message before a first person logs off the computer system. The configured OOO message may then be analyzed to verify that the message complies with a set of rules such as an e-mail policy in a business environment. Consequently, when an e-mail message is received from a second person and the first person is unavailable, an OOO message may be returned to the second person. Different variations of an OOO message may also be selected based on the specifics of the second person.
    Type: Application
    Filed: January 2, 2014
    Publication date: July 2, 2015
    Applicant: Bank of America Corporation
    Inventors: Vipul Seth, Anand Daga, Gurdeep Walia, Narasimhan Raghavendran, Saroj K. Bonthapalli
  • Patent number: 8356270
    Abstract: A system and method for providing a statistical budgeting approach to modeling reliability effects such as interconnect electromigration (EM), transistor time-dependant dielectric breakdown (TDDB), hot-carrier injection effects (HCI) and bias temperature instability (BTI) is disclosed. A static analysis flow captures the effects of design topology, switching constraints, interactions between signal nets and supply rails as well as thermal gradients due to interconnect and transistor self as well as mutual heating, and was used to verify successive iterations of deep sub-micron integrated circuit designs.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: January 15, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tom Burd, Yuri Apanovich, Srinivasaraghavan Krishnamoorthy, Vishak Kumar Venkatraman, Anand Daga
  • Publication number: 20120096424
    Abstract: A system and method for providing a statistical budgeting approach to modeling reliability effects such as interconnect electromigration (EM), transistor time-dependant dielectric breakdown (TDDB), hot-carrier injection effects (HCI) and bias temperature instability (BTI) is disclosed. A static analysis flow captures the effects of design topology, switching constraints, interactions between signal nets and supply rails as well as thermal gradients due to interconnect and transistor self as well as mutual heating, and was used to verify successive iterations of deep sub-micron integrated circuit designs.
    Type: Application
    Filed: October 19, 2010
    Publication date: April 19, 2012
    Inventors: Tom Burd, Yuri Apanovich, Srinivasaraghavan Krishnamoorthy, Vishak Kumar Venkatraman, Anand Daga
  • Patent number: 7425858
    Abstract: A delay line is periodically configured into a delay-locked loop for calibration purposes. That is, the delay line is operated in an open loop mode during a first time period in which a signal, such as an aperiodic signal, is the input signal into the delay line. Periodically, the delay line is configured into a delay-locked loop and the delay line is recalibrated based on a periodic signal supplied to the delay-locked loop.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: September 16, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Anand Daga
  • Patent number: 7271634
    Abstract: A delay-locked loop (DLL) has a counter that is incremented or decremented by the loop in the process of achieving lock. The counter value is converted using an digital to analog converter (DAC) to an analog voltage that controls the delay through the delay line. During faster lock modes, the loop increments/decrements intermediate bits of the counter (with the bits less significant being held at a constant value, e.g., 0) to provide a coarse lock, rather than incrementing/decrementing the least significant bit of the counter. After coarse lock is achieved, a better lock is then achieved by incrementing/decrementing the counter using a smaller increment, i.e., a less significant bit is updated, until finally, the LSB is utilized to achieve fine lock. Utilizing the coarse lock first, and then one or more finer locks, allows the lock to be achieved more quickly.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: September 18, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anand Daga, Sanjay Sethi, Philip E. Madrid
  • Patent number: 7256636
    Abstract: A voltage controlled delay line (VCDL). The VCDL includes one or more cells. Each of the one or more cells includes two or more inputs and an output. Each of the one or more cells is configured to provide a delay as well as an interpolation function and a multiplexer function. The VCDL may be used to provide delay in a delay locked loop (DLL).
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: August 14, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rohit Kumar, Anand Daga, Sanjay Sethi
  • Publication number: 20070075757
    Abstract: A voltage controlled delay line (VCDL). The VCDL includes one or more cells. Each of the one or more cells includes two or more inputs and an output. Each of the one or more cells is configured to provide a delay as well as an interpolation function and a multiplexer function. The VCDL may be used to provide delay in a delay locked loop (DLL).
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Rohit Kumar, Anand Daga, Sanjay Sethi