Patents by Inventor Anand Janaswamy

Anand Janaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120080078
    Abstract: Photovoltaic (PV) crystalline silicon modules and methods of manufacturing wherein the modules contain a non-glass front sheet, upper and lower encapsulate layers, a PV cell layer, an insulating sheet, and a structural back plane comprising an aluminum composite. The front sheet can be comprised of ETFE, the encapsulate layers comprise EVA, and the back plane preferably comprises APA. This particular configuration results in a lightweight PV module that still retains a high power density, and can be readily installed onto rooftops without traditional heavy racking. The PV module may be adhered to the roof using a double sided pressure sensitive adhesive or heat welded.
    Type: Application
    Filed: October 2, 2010
    Publication date: April 5, 2012
    Applicant: APPLIED SOLAR, LLC
    Inventors: Mark Farrelly, Anand Janaswamy, Shewit Agaskar, John Montello
  • Publication number: 20110240337
    Abstract: Various embodiments of the invention provide an interconnect designed to be placed between layers of a photovoltaic laminate, and that has built-in in-plane stress relief features. In accordance with various embodiments, the interconnect, once implemented into a photovoltaic laminate, can withstand at least 200 temperature cycles, as is required by certain certifying bodies, without suffering failure.
    Type: Application
    Filed: April 5, 2010
    Publication date: October 6, 2011
    Inventors: John Montello, Mark Farrelly, Anand Janaswamy, Mike Curtis
  • Publication number: 20100294341
    Abstract: The present invention is directed toward apparatus and methods for solar panels capable of rooftop installation. In some embodiments, a low profile solar laminate is provided, comprising: a base layer; a photovoltaic layer; a semi-rigid panel; an ultraviolet resistant layer; wherein a first adhesive adheres the base layer to the semi-rigid panel, a second adhesive adheres the semi-rigid panel to the photovoltaic layer, and a third adhesive adheres the ultraviolet resistant layer to the photovoltaic layer.
    Type: Application
    Filed: February 2, 2010
    Publication date: November 25, 2010
    Inventors: CHRISTOPHER FRANK, John Montello, Chris Gopal, Mike Curtis, Anand Janaswamy, Mark Farrelly
  • Publication number: 20100101634
    Abstract: The present invention is directed toward apparatuses, systems and methods for solar panels capable of rooftop installation. In some embodiments, a low profile solar panel is provided, comprising: a solar laminate; and a flexible material sheet adhered to the solar laminate, wherein the flexible material sheet is configured to operate as a frame that supports and houses the solar laminate. In some such embodiments, the low profile solar panel further comprises a secondary sheet, wherein the secondary sheet is disposed on an edge formed by adhering the flexible material sheet to the solar laminate.
    Type: Application
    Filed: September 10, 2009
    Publication date: April 29, 2010
    Inventors: CHRISTOPHER FRANK, John Montello, Christopher S. Gopal, Mike Curtis, Anand Janaswamy, Mark Farrelly
  • Patent number: 5666280
    Abstract: A half-bridge driver circuit including a lower drive module and a floating upper drive module for driving respective external upper and lower power transistors of a high voltage half bridge is contained in an integrated circuit chip which includes an on-chip bootstrap diode emulator which is turned on in response to a control signal applied to its gate in order to pass current from a power supply to charge an external bootstrap capacitor that powers the upper drive module. The upper drive module is accommodated in an insulated well and the diode emulator includes as its main current carrying element, a JFET transistor formed along the periphery of the well. The JFET transistor is driven into a conducting state at the same time the lower power transistor is driven into a conducting state.
    Type: Grant
    Filed: December 27, 1995
    Date of Patent: September 9, 1997
    Assignee: Philips Electronics North America Corporation
    Inventors: Anand Janaswamy, Rajsekhar Jayaraman, Michael Amato, Paul R. Veldman
  • Patent number: 5502632
    Abstract: A half-bridge driver circuit including a lower drive module and a floating upper drive module for driving respective external upper and lower power transistors of a high voltage half bridge is contained in an integrated circuit chip which includes an on-chip bootstrap diode emulator for charging an external bootstrap capacitor that powers the upper drive module. The upper drive is accommodated in an insulated well and the diode emulator includes as its main current carrying element, a LDMOS transistor formed along the periphery of the well. The LDMOS transistor is driven into a conducting state at the same time the lower power transistor is driven into a conducting state. A clamp and current source solidly bias the backate of the LDMOS while limiting the current drawn by a parasitic transistor attached to the backgate during startup of the LDMOS.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: March 26, 1996
    Assignee: Philips Electronics North America Corporation
    Inventors: Leo F. P. Warmerdam, Anand Janaswamy
  • Patent number: 5373435
    Abstract: A half-bridge driver circuit including a lower drive module and a floating upper drive module for driving respective external upper and lower power transistors of a high voltage half bridge is contained in an integrated circuit chip which includes an on-chip bootstrap diode emulator for charging an external bootstrap capacitor that powers the upper drive module. The upper drive is accommodated in an insulated well and the diode emulator includes as its main current carrying element, a LDMOS transistor formed along the periphery of the well. The LDMOS transistor is driven into a conducting state at the same time the lower power transistor is driven into a conducting state.
    Type: Grant
    Filed: November 19, 1993
    Date of Patent: December 13, 1994
    Assignee: Philips Electronics North America Corporation
    Inventors: Rajsekhar Jayaraman, Anand Janaswamy, Thor Wacyk