Abstract: A time-interleaved digital-to-analog converter (DAC) architecture is provided. The DAC architecture includes a multiplexer/encoder configured to receive a data signal and to generate a plurality of data streams based on the data signal. First and second DAC circuits receive respective first and second data streams of the plurality of data streams and selectively process the respective first and second data streams to generate a respective DAC output signal. The respective DAC output signals of the first and second DAC circuits are coupled together to provide an output signal of the DAC architecture.

Abstract: A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC units. Each DAC unit is coupled to a respective bit of a digital input. The DAC units are configured to maintain a constant output impedance. Each DAC unit includes one or more complementary switch pairs that couple first nodes of one or more respective impedances to one of the first or the second supply voltage, based on the respective bit of the digital input. Second nodes of the one or more respective impedances are coupled to an output node.

Abstract: A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC units. Each DAC unit is coupled to a respective bit of a digital input. The DAC units are configured to maintain a constant output impedance. Each DAC unit includes one or more complementary switch pairs that couple first nodes of one or more respective impedances to one of the first or the second supply voltage, based on the respective bit of the digital input. Second nodes of the one or more respective impedances are coupled to an output node.

Abstract: A low-power high-swing current-mode logic (CML) driver circuit includes a first differential-pair and a second differential-pair. The first differential-pair includes first transistors, and is coupled to a first voltage supply that supplies a first voltage. The second differential-pair includes second transistors, and a common node of the second differential-pair is coupled to a second voltage supply. The second voltage supply supplies a second voltage that is higher than the first voltage. Control terminals of the first transistors are coupled to control terminals of the second transistors to form input nodes of the driver circuit.

Abstract: Provided is a low latency high bandwidth clock and data recovery (CDR) system. For example, there is a low latency high bandwidth CDR system including a demultiplexer configured to convert a high frequency input datastream to a low frequency output datastream according to a first latency and a phase error processor at least partially embedded into the demultiplexer and configured to determine a datastream phase error of the high frequency input datastream according to a second latency. The embedded phase error processor allows a portion of a total latency of the CDR system due to the demultiplexer and the phase error processor to be less than a sum of the first and second latencies.

Abstract: Provided is a low latency high bandwidth clock and data recovery (CDR) system. For example, there is a low latency high bandwidth CDR system including a demultiplexer configured to convert a high frequency input datastream to a low frequency output datastream according to a first latency and a phase error processor at least partially embedded into the demultiplexer and configured to determine a datastream phase error of the high frequency input datastream according to a second latency. The embedded phase error processor allows a portion of a total latency of the CDR system due to the demultiplexer and the phase error processor to be less than a sum of the first and second latencies.

Abstract: A multi-mode driver and method therefore includes a plurality of amplifiers, an adjustable load block, and adjustable current supply circuitry that selectively adjusts current magnitudes supplied to at least one of the plurality of amplifiers. The multi-mode driver can operate in a KR mode with a higher voltage supply, an SR4 mode with the higher voltage supply, and an SFI mode with a lower voltage supply. To support these modes, the multi-mode driver selectively operates a plurality of amplifiers, adjusts current magnitudes supplied to the amplifiers, and selectively adjusts an adjustable load. Thus, the multi-mode driver is operable to selectively and efficiently produce high swing and low swing output signals and to efficiently operate with any one of a plurality of supplies. The driver includes selectable loads and parallel-coupled amplifier devices that are selected based on mode.

Abstract: A multi-mode driver and method therefore includes a plurality of amplifiers, an adjustable load block, and adjustable current supply circuitry that selectively adjusts current magnitudes supplied to at least one of the plurality of amplifiers. The multi-mode driver can operate in a KR mode with a higher voltage supply, an SR4 mode with the higher voltage supply, and an SFI mode with a lower voltage supply. To support these modes, the multi-mode driver selectively operates a plurality of amplifiers, adjusts current magnitudes supplied to the amplifiers, and selectively adjusts an adjustable load. Thus, the multi-mode driver is operable to selectively and efficiently produce high swing and low swing output signals and to efficiently operate with any one of a plurality of supplies. The driver includes selectable loads and parallel-coupled amplifier devices that are selected based on mode.