Patents by Inventor Anand KHOT
Anand KHOT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10913814Abstract: The present invention relates to an aqueous dispersion based on polyurethane-urea, a composition comprising the same, and a use of the same in a coating agent, a sealant and an adhesive. The aqueous polyurethane-urea dispersion comprises a polyurethane-urea dispersed therein having sulfonate and/or carboxylate groups and lateral carboxyl groups, wherein the amount of said sulfonate and or carboxylate groups is 1.5 to 15 mmol/100 g; said lateral carboxyl is introduced by an aminocarboxylic acid having an amino functionality of greater than 1; the amount of said lateral carboxyl is 1.5 to 9.5 mmol/100 g, based on the polyurethane-urea solid components. Compared with the prior art, the composition of the polyurethane-urea based aqueous dispersion and a carboxyl reactive cross-linking agent provided by the present invention has a good cross-linking property and an excellent heat-resistance, which is not prone to come unglued when being exposed to heat.Type: GrantFiled: December 27, 2016Date of Patent: February 9, 2021Assignee: Covestro Deutschland AGInventors: Chen Jin, Winnie Wei, Evgeny Avtomonov, Anand Khot, Yingdan Zhu
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Patent number: 10678695Abstract: Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.Type: GrantFiled: December 6, 2017Date of Patent: June 9, 2020Assignee: MIPS Tech, LLCInventors: Hugh Jackson, Anand Khot
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Publication number: 20190010272Abstract: The present invention relates to an aqueous dispersion based on polyurethane-urea, a composition comprising the same, and a use of the same in a coating agent, a sealant and an adhesive. The aqueous polyurethane-urea dispersion comprises a polyurethane-urea dispersed therein having sulfonate and/or carboxylate groups and lateral carboxyl groups, wherein the amount of said sulfonate and or carboxylate groups is 1.5 to 15 mmol/100 g; said lateral carboxyl is introduced by an aminocarboxylic acid having an amino functionality of greater than 1; the amount of said lateral carboxyl is 1.5 to 9.5 mmol/100 g, based on the polyurethane-urea solid components. Compared with the prior art, the composition of the polyurethane-urea based aqueous dispersion and a carboxyl reactive cross-linking agent provided by the present invention has a good cross-linking property and an excellent heat-resistance, which is not prone to come unglued when being exposed to heat.Type: ApplicationFiled: December 27, 2016Publication date: January 10, 2019Applicant: Covestro Deutschland AGInventors: CHEN JIN, Winnie WEI, Evgeny AVTOMONOV, Anand KHOT, Yingdan ZHU
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Patent number: 10001997Abstract: Methods and reservation stations for selecting instructions to issue to a functional unit of an out-of-order processor. The method includes classifying each instruction into one of a number of categories based on the type of instruction. Once classified an instruction is stored in an instruction queue corresponding to the category in which it was classified. Instructions are then selected from one or more of the instruction queues to issue to the functional unit based on a relative priority of the plurality of types of instructions. This allows certain types of instructions (e.g. control transfer instructions, flag setting instructions and/or address generation instructions) to be prioritized over other types of instructions even if they are younger.Type: GrantFiled: December 21, 2016Date of Patent: June 19, 2018Assignee: MIPS Tech, LLCInventors: Anand Khot, Hugh Jackson
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Publication number: 20180095885Abstract: Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.Type: ApplicationFiled: December 6, 2017Publication date: April 5, 2018Inventors: Hugh Jackson, Anand Khot
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Patent number: 9910672Abstract: A method and load and store buffer for issuing a load instruction to a data cache. The method includes determining whether there are any unresolved store instructions in the store buffer that are older than the load instruction. If there is at least one unresolved store instruction in the store buffer older than the load instruction, it is determined whether the oldest unresolved store instruction in the store buffer is within a speculation window for the load instruction. If the oldest unresolved store instruction is within the speculation window for the load instruction, the load instruction is speculatively issued to the data cache. Otherwise, the load instruction is stalled until any unresolved store instructions outside the speculation window are resolved. The speculation window is a short window that defines a number of instructions or store instructions that immediately precede the load instruction.Type: GrantFiled: June 15, 2016Date of Patent: March 6, 2018Assignee: MIPS Tech, LLCInventors: Hugh Jackson, Anand Khot
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Patent number: 9858194Abstract: Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.Type: GrantFiled: February 21, 2017Date of Patent: January 2, 2018Assignee: Imagination TechnologiesInventors: Hugh Jackson, Anand Khot
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Publication number: 20170168949Abstract: Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.Type: ApplicationFiled: February 21, 2017Publication date: June 15, 2017Inventors: Hugh Jackson, Anand Khot
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Publication number: 20170102949Abstract: Methods and reservation stations for selecting instructions to issue to a functional unit of an out-of-order processor. The method includes classifying each instruction into one of a number of categories based on the type of instruction. Once classified an instruction is stored in an instruction queue corresponding to the category in which it was classified. Instructions are then selected from one or more of the instruction queues to issue to the functional unit based on a relative priority of the plurality of types of instructions. This allows certain types of instructions (e.g. control transfer instructions, flag setting instructions and/or address generation instructions) to be prioritized over other types of instructions even if they are younger. To be accompanied, when published, by FIG. 2 of the accompanying drawings.Type: ApplicationFiled: December 21, 2016Publication date: April 13, 2017Inventors: Anand Khot, Hugh Jackson
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Patent number: 9612968Abstract: Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.Type: GrantFiled: February 9, 2016Date of Patent: April 4, 2017Assignee: Imagination Technologies LimitedInventors: Hugh Jackson, Anand Khot
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Patent number: 9558001Abstract: Methods and reservation stations for selecting instructions to issue to a functional unit of an out-of-order processor. The method includes classifying each instruction into one of a number of categories based on the type of instruction. Once classified an instruction is stored in an instruction queue corresponding to the category in which it was classified. Instructions are then selected from one or more of the instruction queues to issue to the functional unit based on a relative priority of the plurality of types of instructions. This allows certain types of instructions (e.g. control transfer instructions, flag setting instructions and/or address generation instructions) to be prioritized over other types of instructions even if they are younger.Type: GrantFiled: July 25, 2014Date of Patent: January 31, 2017Assignee: Imagination Technologies LimitedInventors: Anand Khot, Hugh Jackson
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Publication number: 20160291976Abstract: A method and load and store buffer for issuing a load instruction to a data cache. The method includes determining whether there are any unresolved store instructions in the store buffer that are older than the load instruction. If there is at least one unresolved store instruction in the store buffer older than the load instruction, it is determined whether the oldest unresolved store instruction in the store buffer is within a speculation window for the load instruction. If the oldest unresolved store instruction is within the speculation window for the load instruction, the load instruction is speculatively issued to the data cache. Otherwise, the load instruction is stalled until any unresolved store instructions outside the speculation window are resolved. The speculation window is a short window that defines a number of instructions or store instructions that immediately precede the load instruction.Type: ApplicationFiled: June 15, 2016Publication date: October 6, 2016Inventors: Hugh Jackson, Anand Khot
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Patent number: 9395991Abstract: A method and load and store buffer for issuing a load instruction to a data cache. The method includes determining whether there are any unresolved store instructions in the store buffer that are older than the load instruction. If there is at least one unresolved store instruction in the store buffer older than the load instruction, it is determined whether the oldest unresolved store instruction in the store buffer is within a speculation window for the load instruction. If the oldest unresolved store instruction is within the speculation window for the load instruction, the load instruction is speculatively issued to the data cache. Otherwise, the load instruction is stalled until any unresolved store instructions outside the speculation window are resolved. The speculation window is a short window that defines a number of instructions or store instructions that immediately precede the load instruction.Type: GrantFiled: January 31, 2014Date of Patent: July 19, 2016Assignee: Imagination Technologies LimitedInventors: Hugh Jackson, Anand Khot
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Publication number: 20160154740Abstract: Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.Type: ApplicationFiled: February 9, 2016Publication date: June 2, 2016Inventors: Hugh Jackson, Anand Khot
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Patent number: 9292450Abstract: Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.Type: GrantFiled: February 25, 2014Date of Patent: March 22, 2016Assignee: Imagination Technologies LimitedInventors: Hugh Jackson, Anand Khot
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Publication number: 20150154022Abstract: Soft-partitioning of a register file cache is implemented by renaming registers associated with an instruction based on which thread, in a multi-threaded out-of-order processor, the instruction belongs to. The register renaming may be performed by a register renaming module and in an embodiment, the register renaming module receives an instruction for register renaming which identifies the thread associated with the instruction and one or more architectural registers. Available physical registers are then allocated to each identified architectural register based on the identified thread. In some examples, the physical registers in the multi-threaded out-of order processor are logically divided into groups and physical registers are allocated based on a thread to group mapping. In further examples, the thread to group mapping is not fixed but may be updated based on the activity level of one or more threads in the multi-threaded out-of-order processor.Type: ApplicationFiled: November 19, 2014Publication date: June 4, 2015Inventors: Anand Khot, Hugh Jackson
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Publication number: 20150106595Abstract: Methods and reservation stations for selecting instructions to issue to a functional unit of an out-of-order processor. The method includes classifying each instruction into one of a number of categories based on the type of instruction. Once classified an instruction is stored in an instruction queue corresponding to the category in which it was classified. Instructions are then selected from one or more of the instruction queues to issue to the functional unit based on a relative priority of the plurality of types of instructions. This allows certain types of instructions (e.g. control transfer instructions, flag setting instructions and/or address generation instructions) to be prioritized over other types of instructions even if they are younger.Type: ApplicationFiled: July 25, 2014Publication date: April 16, 2015Inventors: Anand Khot, Hugh Jackson
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Publication number: 20140258627Abstract: Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.Type: ApplicationFiled: February 25, 2014Publication date: September 11, 2014Applicant: IMAGINATION TECHNOLOGIES LIMITEDInventors: Hugh Jackson, Anand Khot
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Publication number: 20140229718Abstract: A method and load and store buffer for issuing a load instruction to a data cache. The method includes determining whether there are any unresolved store instructions in the store buffer that are older than the load instruction. If there is at least one unresolved store instruction in the store buffer older than the load instruction, it is determined whether the oldest unresolved store instruction in the store buffer is within a speculation window for the load instruction. If the oldest unresolved store instruction is within the speculation window for the load instruction, the load instruction is speculatively issued to the data cache. Otherwise, the load instruction is stalled until any unresolved store instructions outside the speculation window are resolved. The speculation window is a short window that defines a number of instructions or store instructions that immediately precede the load instruction.Type: ApplicationFiled: January 31, 2014Publication date: August 14, 2014Applicant: IMAGINATION TECHNOLOGIES, LTD.Inventors: Hugh JACKSON, Anand KHOT