Abstract: Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.

Abstract: A switchable thermal circuit breaker (10) has an automatically resettable, current carrying thermostatic disc (14) cantilever mounted in a housing (12) and carries a movable contact (14b) into and out of electrical engagement with a stationary contact (14c). A disc coupling member (16) is pivotally mounted above the disc and has fingers (16e, 16f) to capture opposed sides of the disc so that the disc coupling member pivots concomitantly with movement of the disc. A radially extending blade (18c) of a pivot member is biased by a spring (18k) into engagement with a stop surface (16k) of the disc coupling member when the contacts are in the engaged position and is movable under the stop arm (16g) when the disc moves to the contacts disengaged position to prevent reengagement of the contacts.

Abstract: The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.

Abstract: During a Built-In Self-Test (BIST) routine, execution of a sequence of tests is re-initiated after a corrective action is taken starting with the test having the highest re-ordered priority. The test having the highest re-ordered priority corresponds to a test in a sequence of tests that detected the error corresponding to the corrective action taken or a related test in the case where the test that detected the error is dependent upon results generated by the related test. According to one embodiment, a BIST routine is executed by initiating execution of a sequence of tests configured to detect errors and, after a corrective action is taken in response to one or more of the errors being detected, re-initiating execution of the sequence of tests starting with the test that detected the error corresponding to the corrective action most recently taken.

Abstract: Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.

Abstract: A multi-port memory array is tested by simultaneously writing data to the array via two or more write ports, and/or simultaneously reading data from the array via two or more read ports, at the processor operating frequency. Comparing the data read from the array to that written to the array may be performed sequentially or in parallel. Comparator circuits are effectively disabled during normal processor operations. By simultaneously writing and/or reading data via multiple ports, latent electrical marginalities may be exposed. In addition, writing test patterns using multiple write ports and reading the patterns using multiple read ports significantly reduces test time during semiconductor manufacturing tests.

Abstract: A switchable thermal circuit breaker (10) has an automatically resettable, current carrying thermostatic disc (14) cantilever mounted in a housing (12) and carries a movable contact (14b) into and out of electrical engagement with a stationary contact (14c). A disc coupling member (16) is pivotally mounted above the disc and has fingers (16e, 16f) to capture opposed sides of the disc so that the disc coupling member pivots concomitantly with movement of the disc. A radially extending blade (18c) of a pivot member is biased by a spring (18k) into engagement with a stop surface (16k) of the disc coupling member when the contacts are in the engaged position and is movable under the stop arm (16g) when the disc moves to the contacts disengaged position to prevent reengagement of the contacts.

Abstract: A wear resistant coating including a hard backing including a metal alloy matrix dispersed with a plurality of hard particles; and a plurality of nano-layers disposed on the hard backing is provided. The plurality of nano-layers has different characteristics from one another. A method of making a wear resistant coating is provided. The method includes the steps of providing a substrate; disposing a hard backing; and disposing a plurality of nano-layers on the hard backing.

Abstract: The invention relates to a method for controlling data traffic in a telecommunications network (150), said control being carried out in terms of a statistic modeling of the traffic transmitted by the network (150) by means of a gaussian distribution of the data flow. According to the invention, one such method is characterized in that a characteristic value of the Gaussian distribution is weighted by means of a parameter ? which varies according to the intensity of the variations or the discontinuity, of the traffic process by said network (150), said weighted value being used to evaluate the traffic in the network.

Abstract: A method for remotely enhancing a picture archiving communication system (PACS) is provided. The method includes establishing an Internet connection with a server. The method also includes directing the server to simultaneously install software to a plurality of PACS workstations and simultaneously installing software to the plurality of PACS workstations. The method may optionally include, in the directing step, instructing the server to install at least one software update to the plurality of workstations. The method may also optionally include, in the establishing step, logging on to a web server and authenticating a user, and sending an indication message to a remote user to indicate whether the software installation was successful. An alternative embodiment provides an apparatus for remotely enhancing a picture archiving communication system. In another exemplary embodiment of the invention, a method for remotely monitoring a picture archiving communication system (PACS) is provided.

Abstract: The present invention provides a workflow for patient scheduling in a Hospital Information System (HIS). While diagnosing a medical problem of a patient, a referring physician may refer a patient for certain exams. The referring physician places a request for ordering the exams with a scheduler that sent to the scheduler in the form of a decision tree. The decision tree includes a first set of exams and additional exams to be performed on a patient. The scheduler orders the exams by scheduling the exams with an acquisition modality and informs the patient about the schedule of the exams. The exams are performed on the patient and medical information from the exams is stored in an archive. The information is also sent to an analyst for analysis. The analyst analyzes the medical images and orders additional exams mentioned in the decision tree based on the results of an exam. The analyst requests additional exams until an end of the decision tree is reached.

Abstract: A router of a communication network, for example an Internet Protocol communication network, comprises processors for determining its internal load status and, on receiving a flow of packets of data associated with a traffic class, assigning certain internal resources of the router to the received flow as a function of the traffic class of the flow and the determined load status of the router.

Abstract: A disjoint graph structure for packet classification in communication systems is presented. The disjoint graph is comprised of two types of data structures; an elementary interval tree (EIT) and a disjoint interval tree (DIT). The disjoint graph is constructed based on a range-specified rule set finding particular application in the classification of data packets. Each rule in the rule set has an equal number of fields and each field specifies a range referred to as an integer interval having a lower and an upper bound. The disjoint graph has the same number of layers as there are fields in each rule. The layers are comprised of nodes, and each node has an associated rule set selected from the range-specified rule set. The disjoint graph enables packet classification in only one pass through the tree. The EIT and DIT structures are also presented in detail.

Abstract: A method and apparatus for displaying annotations on a digital image such that the viewing area is simplified and maximized. Abbreviated reason codes are employed, thereby increasing the number of annotations that may be displayed concurrently with an image and reducing the obtrusiveness of the annotations. The abbreviated reason codes may provide information to viewers about the significance of the image. Viewers may configure where the annotations are displayed and may associate priorities with the reason codes such that annotations of interest may be displayed more prominently or accessibly. Likewise, text descriptions associated with an annotation may be hidden until requested by a viewer. In instances where the number of annotations exceeds some configurable threshold, the excess annotations may be hidden unless requested.