Abstract: An apparatus includes an amplifier configured to compare a feedback input, corresponding to a voltage of an output voltage node, with respect to a reference input and to provide a control output to control the output voltage node based on a difference between the feedback input and the reference input. At least two source circuits are coupled with the output voltage node. Each of the source circuits are configured to provide respective voltage sources to supply electrical power to the output voltage node.

Abstract: Methods, devices, apparatuses, and systems may provide integrated combined current sensing for parallel charging architecture. In one embodiment a charger includes a first charging device that includes a switching circuit having a switching output configured to be coupled to a first terminal of an inductive element. The first charging device further includes a charging terminal configured to couple a second terminal of the inductive element to a battery terminal to provide a first power source to charge a battery coupled to the battery terminal. The first charging device further includes a charge current sense element coupled between the charging terminal and the second terminal of the inductive element. The charge current sense element is configured to sense a charge current at the charging terminal.

Abstract: An apparatus includes an amplifier configured to compare a feedback input, corresponding to a voltage of an output voltage node, with respect to a reference input and to provide a control output to control the output voltage node based on a difference between the feedback input and the reference input. At least two source circuits are coupled with the output voltage node. Each of the source circuits are configured to provide respective voltage sources to supply electrical power to the output voltage node.

Abstract: Methods, devices, apparatuses, and systems may provide integrated combined current sensing for parallel charging architecture. In one embodiment a charger includes a first charging device that includes a switching circuit having a switching output configured to be coupled to a first terminal of an inductive element. The first charging device further includes a charging terminal configured to couple a second terminal of the inductive element to a battery terminal to provide a first power source to charge a battery coupled to the battery terminal. The first charging device further includes a charge current sense element coupled between the charging terminal and the second terminal of the inductive element. The charge current sense element is configured to sense a charge current at the charging terminal.

Abstract: Power supplies combining a switching-mode power supply in parallel with a current source can improve maximum load current capability. The current source can be turned on, or the amount of current supplied by the current source increased, when there is a heavy load current demand, for example, when the load current demand is more than the current rating of the switching-mode power supply. The duty cycle of the output stage of the switching-mode power supply can be used to determine the load current demand. The current source may increase the maximum output current of the power supply beyond the maximum output current of the switching-mode power supply. For example, the current source may add 0.5 A to the current capability of a 2.5 A switching-mode power supply.

Abstract: Power supplies combining a switching-mode power supply in parallel with a current source can improve maximum load current capability. The current source can be turned on, or the amount of current supplied by the current source increased, when there is a heavy load current demand, for example, when the load current demand is more than the current rating of the switching-mode power supply. The duty cycle of the output stage of the switching-mode power supply can be used to determine the load current demand. The current source may increase the maximum output current of the power supply beyond the maximum output current of the switching-mode power supply. For example, the current source may add 0.5 A to the current capability of a 2.5 A switching-mode power supply.

Abstract: Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. Depending on the binary data ‘1’ or ‘0’ to be transmitted, ‘M’ or ‘M+1’ clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used to generate N pulse width modulated (PWM) phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize a sine waveform whose lower harmonics are substantially suppressed.

Abstract: Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. Depending on the binary data ‘1’ or ‘0’ to be transmitted, ‘M’ or ‘M+1’ clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used to generate N pulse width modulated (PWM) phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize a sine waveform whose lower harmonics are substantially suppressed.