Patents by Inventor Anand Kulkarni

Anand Kulkarni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11281601
    Abstract: Example multi-device storage systems, storage devices, and methods provide hosted services on peer storage devices. Storage devices include a storage medium, a logical mapping memory, and a processor for executing hosted services using the logical mapping memory. Each storage device is configured to communicate with peer storage devices over an interconnect fabric. The logical mapping memory includes storage device media logical mapping information configured in continuous logical blocks with a media block size equal to a page programming size of the storage medium. The logical mapping memory also includes host logical mapping information, configured in host logical blocks with a host block size smaller than the media block size, for the peer storage devices.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: March 22, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sanjay Subbarao, Vladislav Bolkhovitin, Anand Kulkarni, Brian Walter O'Krafka
  • Patent number: 11248473
    Abstract: A turbine blade includes a platform with an internal cavity formed therein and an airfoil extending radially from the platform. The turbine blade includes a first portion made from ceramic matrix composite materials and a second portion made from superalloy materials. The first and second portions are selectively connected to each other via a spur and include an internal cooling circuit extending across both the first and second portions for circulating coolant therethrough. At least one supply passage extends between the internal cooling circuit and the internal platform cavity and includes an array of pin fins and turbulators for diverting coolant to the internal platform cavity.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: February 15, 2022
    Assignee: Siemens Energy, Inc.
    Inventors: Arindam Dasgupta, Anand A. Kulkarni
  • Publication number: 20220031237
    Abstract: The invention provides systems, methods and computer program products for monitoring vascular perfusion in replanted tissue flaps. Specifically, the invention provides a non-invasive solution for monitoring of vascular perfusion at a site of tissue replantation, and that is capable of detecting problems in vascular perfusion and raising alarms in real times. The invention achieves the above function objectives by means of non-invasive sensors that continuously monitor selected parameters related to tissue condition. The monitored data parameters are used to determine a real time condition of replanted tissue.
    Type: Application
    Filed: December 2, 2019
    Publication date: February 3, 2022
    Inventors: Nirmal Kumar, Aniket Anand Kulkarni, Deepika Dixit, Yasuyuki Matsuura, Prashant Jha, Ashish Bichpuriya
  • Publication number: 20210397930
    Abstract: A non-volatile memory device includes an array of non-volatile memory cells that are configured to store weights of a neural network. Associated with the array is a data latch structure that includes a page buffer, which can store weights for a layer of the neural network that is read out of the array, and a transfer buffer, that can store inputs for the neural network. The memory device can perform multiply and accumulate operations between inputs and weight of the neural network within the latch structure, avoiding the need to transfer data out of the array and associated latch structure for portions of an inference operation. By using binary weights and inputs, multiplication can be performed by bit-wise XNOR operations. The results can then be summed and activation applied, all within the latch structure.
    Type: Application
    Filed: June 22, 2020
    Publication date: December 23, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Anand Kulkarni, Won Ho Choi, Martin Lueker-Boden
  • Patent number: 11174557
    Abstract: Materials and a process for forming a protective oxide coating. The high temperature coating system (108) includes at least a thermal barrier coating layer (104) and a thermally stable, deposit resistant protective layer (106) on the thermal barrier coating layer (104).
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: November 16, 2021
    Assignee: Siemens Energy Global GmbH & Co. KG
    Inventors: Anand A. Kulkarni, Atin Sharma
  • Publication number: 20210342671
    Abstract: A non-volatile memory structure capable of storing layers of a deep neural network (DNN) and perform an inferencing operation within the structure is presented. A stack of bonded die pairs is connected by through silicon vias. Each bonded die pair includes a memory die, having one or more memory arrays onto which layers of the neural network are mapped, and a peripheral circuitry die, including the control circuits for performing the convolution or multiplication for the bonded die pair. The multiplications can either be done in-array on the memory die or in-logic on the peripheral circuitry die. The arrays can be formed into columns along the vias, allowing an inferencing operation to be performed by propagating an input up and down the columns, with the output of one level being the input of the subsequent layer.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 4, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Tung Thanh Hoang, Martin Lueker-Boden, Anand Kulkarni
  • Publication number: 20210342676
    Abstract: Anon-volatile memory structure capable of storing layers of a deep neural network (DNN) and perform an inferencing operation within the structure is presented. A stack of bonded die pairs is connected by through silicon vias. Each bonded die pair includes a memory die, having one or more memory arrays onto which layers of the neural network are mapped, and a peripheral circuitry die, including the control circuits for performing the convolution or multiplication for the bonded die pair. The multiplications can either be done in-array on the memory die or in-logic on the peripheral circuitry die. The arrays can be formed into columns along the vias, allowing an inferencing operation to be performed by propagating an input up and down the columns, with the output of one level being the input of the subsequent layer.
    Type: Application
    Filed: June 12, 2020
    Publication date: November 4, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Tung Thanh Hoang, Martin Lueker-Boden, Anand Kulkarni
  • Publication number: 20210303909
    Abstract: A system with a multiplication circuit having a plurality of multipliers is disclosed. Each of the plurality of multipliers is configured to receive a data value and a weight value to generate a product value in a convolution operation of a machine learning application. The system also includes an accumulator configured to receive the product value from each of the plurality of multipliers and a register bank configured to store an output of the convolution operation. The accumulator is further configured to receive a portion of values stored in the register bank and combine the received portion of values with the product values to generate combined values. The register bank is further configured to replace the portion of values with the combined values.
    Type: Application
    Filed: March 25, 2020
    Publication date: September 30, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Kiran Gunnam, Anand Kulkarni, Zvonimir Bandic
  • Publication number: 20210303976
    Abstract: An apparatus includes a tensor compute cluster having a plurality of tensor compute units to process a plurality of sub-feature maps in a machine learning application and a tensor memory cluster having a plurality of tensor feature map memory units to store the plurality of sub-feature maps. The apparatus also includes circuitry to partition an input feature map into the plurality of sub-feature maps such that sparsity in each of the plurality of sub-feature maps satisfies a predetermined threshold, and assign each of the plurality of sub-feature maps to one of the plurality of tensor compute units and one of the plurality of tensor feature map memory units for processing in parallel.
    Type: Application
    Filed: March 25, 2020
    Publication date: September 30, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Kiran Gunnam, Anand Kulkarni, Zvonimir Bandic
  • Publication number: 20210279853
    Abstract: A computer-implemented method for assessing material microstructure of a machine component involves obtaining a raw image of a section of the component captured via a microscope. The method further includes pre-processing the raw image to generate a ternary image defined by pixel data including three levels of intensities. The method further includes identifying, from the ternary image, phase boundaries delineating at a phase in a primary constituent material of the component. The method further includes determining a volume associated with the phase based on the identified phase boundaries. The proposed method may be utilized, for example, as an automated tool for assessing material degradation and for quality control of gas turbine engine components.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 9, 2021
    Inventors: Arindam Dasgupta, Biswadip Dey, Anand A. Kulkarni, Amit Chakraborty
  • Patent number: 11081474
    Abstract: Systems and methods for dynamically assigning memory array die to CMOS die of a plurality of stacked die during memory operations are described. The plurality of stacked die may be vertically stacked and connected together via one or more vertical through-silicon via (TSV) connections. The memory array die may only comprise memory cell structures (e.g., vertical NAND strings) without column decoders, row decoders, charge pumps, sense amplifiers, control circuitry, page registers, or state machines. The CMOS die may contain support circuitry necessary for performing the memory operations, such as read and write memory operations. The one or more vertical TSV connections may allow each memory array die of the plurality of stacked die to communicate with or be electrically connected to one or more CMOS die of the plurality of stacked die.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 3, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Tung Thanh Hoang, Martin Lueker-Boden, Anand Kulkarni
  • Publication number: 20210199052
    Abstract: A support housing for use in distributing fuel in a gas turbine engine includes a main body defining an inlet aperture, a plurality of outlet apertures, and a substantially planar mounting surface. A first fuel channel has a wall that defines a first flow space and a support member extends across the first flow space and has a long axis oriented at an oblique angle with respect to the mounting surface.
    Type: Application
    Filed: May 1, 2018
    Publication date: July 1, 2021
    Inventors: Anand A. Kulkarni, Charalambos Polyzopoulos
  • Publication number: 20210191733
    Abstract: An apparatus includes a first tensor compute cluster configured to receive first input feature tensors, a second tensor compute cluster configured to receive second input feature tensors more sparse than the first input feature tensors, and a vector accelerator. The apparatus also includes circuitry configured to partition an input feature map into a plurality of input feature tensors based on a compression criteria and assign each of the plurality of input feature tensors to one of the first tensor compute cluster, the second tensor compute cluster, or the vector accelerator based upon at least one of parameters including a sparsity and an optimization parameter.
    Type: Application
    Filed: December 23, 2019
    Publication date: June 24, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Kiran Gunnam, Anand Kulkarni, Zvonimir Bandic
  • Patent number: 11028704
    Abstract: A turbine blade having an airfoil portion includes a first ceramic matrix composite (CMC) component having a first outer surface and a second ceramic matrix composite (CMC) component having a second outer surface. The second CMC component is positioned adjacent the first CMC component such that the first outer surface and the second outer surface align with one another and at least partially define the airfoil portion. A ceramic bead is at least partially formed at an interface between the first CMC component and the second CMC component. The formation of the bead melts a portion of the first CMC component and the second CMC component, such that the ceramic bead, the first CMC component, and the second CMC component become a single contiguous component and the bead fixedly attaches the first CMC component and the second CMC component.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: June 8, 2021
    Assignee: Siemens Energy, Inc.
    Inventors: Arindam Dasgupta, Anand A. Kulkarni, Ahmed Kamel
  • Patent number: 11028782
    Abstract: A pressure relief arrangement for a gas turbine engine comprises a hinged door and a mount. A plastically deformable member is provided between and coupled to the hinged door and the mount. The deformable member is configured to deform between a non-deformed state when the door is in a closed position and an elongated deformed state when the door is in an open position.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: June 8, 2021
    Inventors: Simon M. Ruston, Rong Yang, Matthew Fox, Aniket Anand Kulkarni
  • Patent number: 10860508
    Abstract: Data management functions are offloaded from a main controller to individual storage devices in a multi-device storage environment. The main controller receives a data management request from a host system, and responds by determining one or more storage devices and one or more data management operations to be performed by the one or more storage devices. The main controller initiates performance of a data management function corresponding to the data management request, by sending one or more data management commands to the one or more storage devices, and initiating one or more data transfers, such as a direct memory access operation to transfer data between a memory buffer of a storage device and a host memory buffer of the host system, and an internal data transfer between two or more of the storage devices using an internal communication fabric of the data storage subsystem.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: December 8, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Vladislav Bolkhovitin, Sanjay Subbarao, Brian W. O'Krafka, Anand Kulkarni, Warren Fritz Kruger
  • Patent number: 10853536
    Abstract: This invention presents a transformative design decision support tool (an e-Design Assessment Engine), one that 1. Significantly reduces cost and risk of engineering design projects, over the state of affair, in part through early and automatic detection of design oversights; 2. Offers compelling reduction in the development time of designs, through improved productivity, but without compromising quality or creativity; 3. Offers wide range of flexibility in terms of supporting design processes employed at different design organizations. The design oversights are identified through proper structuring of the engineering design requirements, extraction of relevant design parameters through application program interfaces provided by the pertinent design tools, and mapping against the requirements. Big data analytics are applied to repositories of past designs, for the purpose of improving new designs.
    Type: Grant
    Filed: June 3, 2017
    Date of Patent: December 1, 2020
    Assignee: Imagars LLC
    Inventors: Baldur Andrew Steingrimsson, Anand Kulkarni
  • Patent number: 10831603
    Abstract: Methods, systems, and other aspects for reconstructing data and rebuilding a failed storage device in a storage system using one or more functioning compute resources and/or storage resources of the failed storage device. For example, a method may include, responsive to a detection of a failed storage device in a storage system, locating data and redundancy information in functioning storage device(s) in the storage system for reconstructing data of the failed storage device; issuing peer-to-peer commands to the functioning storage device(s) to obtain the data and the redundancy information from the functioning storage device(s); and reconstructing the data of the failed storage device based on the data and the redundancy information obtained from the functioning storage device(s), wherein a functioning compute resource of the failed computing device at least partially performs one or more of the locating, issuing, and reconstructing.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: November 10, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Anand Kulkarni, Vladislav Bolkhovitin, Brian Walter O'Krafka, Sanjay Subbarao
  • Patent number: 10824526
    Abstract: Methods, systems, and other aspects for using a failed storage device in a peer-to-peer (P2P) storage system to perform a storage-centric task. For example, a method may include, responsive to a detection of a failed storage device in a P2P storage system, determining, by the failed storage device, that a storage-centric task is assigned to the failed storage device; and performing, by the failed storage device, the storage-centric task responsive to P2P communications with a functioning storage device in the P2P storage system.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: November 3, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Anand Kulkarni, Vladislav Bolkhovitin
  • Publication number: 20200327074
    Abstract: Example multi-device storage systems, storage devices, and methods provide hosted services on peer storage devices. Storage devices include a storage medium, a logical mapping memory, and a processor for executing hosted services using the logical mapping memory. Each storage device is configured to communicate with peer storage devices over an interconnect fabric. The logical mapping memory includes storage device media logical mapping information configured in continuous logical blocks with a media block size equal to a page programming size of the storage medium. The logical mapping memory also includes host logical mapping information, configured in host logical blocks with a host block size smaller than the media block size, for the peer storage devices.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 15, 2020
    Inventors: Sanjay Subbarao, Vladislav Bolkhovitin, Anand Kulkarni, Brian Walter O'Krafka