Patents by Inventor Anand Misra

Anand Misra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230409395
    Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.
    Type: Application
    Filed: June 20, 2023
    Publication date: December 21, 2023
    Applicant: SambaNova Systems, Inc.
    Inventors: Ravinder KUMAR, Conrad Alexander TURLIK, Arnav GOEL, Qi ZHENG, Raghunath SHENBAGAM, Anand MISRA, Ananda Reddy VAYYALA
  • Patent number: 11809908
    Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: November 7, 2023
    Assignee: SambaNova Systems, Inc.
    Inventors: Ravinder Kumar, Conrad Alexander Turlik, Arnav Goel, Qi Zheng, Raghunath Shenbagam, Anand Misra, Ananda Reddy Vayyala
  • Patent number: 11782760
    Abstract: A method for executing applications in a system comprising general hardware and reconfigurable hardware includes accessing a first execution file comprising metadata storing a first priority indicator associated with a first application, and a second execution file comprising metadata storing a second priority indicator associated with a second application. In an example, use of the reconfigurable hardware is interleaved between the first application and the second application, and the interleaving is scheduled to take into account (i) workload of the reconfigurable hardware and (ii) the first priority indicator and the second priority indicator associated with the first application and the second application, respectively. In an example, when the reconfigurable hardware is used by one of the first and second applications, the general hardware is used by another of the first and second applications.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: October 10, 2023
    Assignee: SambaNova Systems, Inc.
    Inventors: Anand Misra, Arnav Goel, Qi Zheng, Raghunath Shenbagam, Ravinder Kumar
  • Publication number: 20230297527
    Abstract: A system is presented that includes two data processing systems that are coupled via a network, each data processing system including a reconfigurable processor with a reconfigurable processor memory, a host that is coupled to the reconfigurable processor and that includes a host processor and a host memory that is coupled to the host processor, and a network interface controller (NIC) that is operatively coupled to the reconfigurable processor and to the host processor. The reconfigurable processor of one of the data processing systems is configured to implement a virtual function that uses a virtual address for a memory access operation. An application programming interface (API) in the host processor translates the virtual address into a physical address, and the NIC uses the physical address to initiate a direct memory access operation at the reconfigurable processor memory or the host memory of the other data processing system.
    Type: Application
    Filed: March 14, 2023
    Publication date: September 21, 2023
    Applicant: SambaNova Systems, Inc.
    Inventors: Conrad Alexander TURLIK, Sudhakar DINDUKURTI, Anand MISRA, Arjun SABNIS, Milad SHARIF, Ravinder KUMAR, Joshua Earle POLZIN, Arnav GOEL, Steven DAI
  • Patent number: 11487694
    Abstract: A data processing system comprises a pool of reconfigurable data flow resources with arrays of physical configurable units, a controller, and a runtime processor. The controller is configured to generate a hot-plug event in response to detecting a removal of an unallocated array of physical configurable units from the pool of reconfigurable data flow resources. The runtime processor is configured to execute user applications on a subset of the arrays of physical configurable units and to receive the hot-plug event from the controller. The runtime processor is further configured to make the removed unallocated array of physical configurable units unavailable for subsequent allocations of subsequent virtual data flow resources and subsequent executions of subsequent user applications, while the subset of the arrays of physical configurable units continues the execution of the user applications.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: November 1, 2022
    Assignee: SambaNova Systems, Inc.
    Inventors: Anand Misra, Conrad Alexander Turlik, Maran Wilson, Anand Vayyala, Raghu Shenbagam, Ranen Chatterjee, Pushkar Shridhar Nandkar, Shivam Raikundalia
  • Publication number: 20220269534
    Abstract: A method for executing applications in a system comprising general hardware and reconfigurable hardware includes accessing a first execution file comprising metadata storing a first priority indicator associated with a first application, and a second execution file comprising metadata storing a second priority indicator associated with a second application. In an example, use of the reconfigurable hardware is interleaved between the first application and the second application, and the interleaving is scheduled to take into account (i) workload of the reconfigurable hardware and (ii) the first priority indicator and the second priority indicator associated with the first application and the second application, respectively. In an example, when the reconfigurable hardware is used by one of the first and second applications, the general hardware is used by another of the first and second applications.
    Type: Application
    Filed: February 25, 2021
    Publication date: August 25, 2022
    Applicant: SambaNova Systems, Inc.
    Inventors: Anand MISRA, Arnav GOEL, Qi ZHENG, Raghunath SHENBAGAM, Ravinder KUMAR
  • Publication number: 20220012077
    Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.
    Type: Application
    Filed: July 7, 2020
    Publication date: January 13, 2022
    Applicant: SambaNova Systems, Inc.
    Inventors: Ravinder KUMAR, Conrad Alexander TURLIK, Arnav GOEL, Qi ZHENG, Raghunath SHENBAGAM, Anand MISRA, Ananda Reddy VAYYALA
  • Patent number: 10725519
    Abstract: Power systems and methods for supplying direct current power to a server rack via a power shelf assembly that includes multiple power supply units (PSUs) and a power shelf controller (PSC) that ensures a correct configuration of PSUs, backup battery units (BBUs), and connection components using a power shelf configuration record. Upon a boot cycle of the PSC, the configuration identified in the power shelf controller is compared to an actual configuration of the components being connected between a server rack and the power shelf assembly to avoid providing power too soon and causing an overload of components for the server rack.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: July 28, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Anand Misra, Vijay Patel, Prashant Singh, Roey Rivnay