Abstract: A system and method for processing graphics are provided. Pixel data may be received for a pixel block. Endpoints for the values of the pixels in the pixel block may be determined. A weight for the pixels in the pixel block may be determined in four dimensions corresponding to the endpoints. A compressed data block representative of the pixel block may be generated in response to the endpoints for the pixel block and the weight for the pixels of the pixel block in the four dimensions corresponding to the endpoints.

Abstract: A system and method for processing graphics are provided. Pixel data may be received for a pixel block. Endpoints for the values of the pixels in the pixel block may be determined. A weight for the pixels in the pixel block may be determined in four dimensions corresponding to the endpoints. A compressed data block representative of the pixel block may be generated in response to the endpoints for the pixel block and the weight for the pixels of the pixel block in the four dimensions corresponding to the endpoints.

Abstract: A method and system for processing video data using multi-pixel scaling in a memory system are provided. The multi-pixel scaling may include reading pixel data for one or more data streams from the memory system into one or more scalers, wherein each of the plurality of data streams includes a plurality of pixels, scaling the pixel via the one or more scalers and outputting the scaled pixels from the one or more scalers. Pixel data may be sequential or parallel. The plurality of scalers may be in parallel, scaling sequential pixel data with independent phase control, or scaling parallel pixel data in substantially equal phase. Pixel data may be transposed, replicated, distributed and aligned prior to reading by scalers, and may be aligned merged and transposed after scaling. Scaling may include interpolation or sub sampling using pixel phase, position, step size and scaler quantities.

Abstract: A method and system for processing video data using multi-pixel scaling in a memory system are provided. The multi-pixel scaling may include reading pixel data for one or more data streams from the memory system into one or more scalers, wherein each of the plurality of data streams includes a plurality of pixels, scaling the pixel via the one or more scalers and outputting the scaled pixels from the one or more scalers. Pixel data may be sequential or parallel. The plurality of scalers may be in parallel, scaling sequential pixel data with independent phase control, or scaling parallel pixel data in substantially equal phase. Pixel data may be transposed, replicated, distributed and aligned prior to reading by scalers, and may be aligned merged and transposed after scaling. Scaling may include interpolation or sub sampling using pixel phase, position, step size and scaler quantities.

Abstract: A method and system for processing video data using multi-pixel scaling in a memory system are provided. The multi-pixel scaling may include reading pixel data for one or more data streams from the memory system into one or more scalers, wherein each of the plurality of data streams includes a plurality of pixels, scaling the pixel via the one or more scalers and outputting the scaled pixels from the one or more scalers. Pixel data may be sequential or parallel. The plurality of scalers may be in parallel, scaling sequential pixel data with independent phase control, or scaling parallel pixel data in substantially equal phase. Pixel data may be transposed, replicated, distributed and aligned prior to reading by scalers, and may be aligned merged and transposed after scaling. Scaling may include interpolation or sub sampling using pixel phase, position, step size and scaler quantities.

Abstract: Flesh-tones corrections may be performed to correct color shifts that may occur in transmitted video frames wherein chroma information corresponding to flesh-tone video pixels may be distorted. A target region may be determined based on a determined flesh-tones region within a spatial representation of chroma in video color space, such as Y?CrCb. The flesh-tones correction may utilize one or more methodologies based on an elliptical shape and/or a triangular shape algorithm(s). A video processing system may be utilized to analyze chroma information of received video pixels and/or to perform flesh-tones corrections by shifting the chroma value of received video pixels towards good flesh-tones regions to compensate for possible distortions. The video processing system may perform conversion calculation and/or shift operations dynamically. The video processing system may also utilize lookup tables (LUTs) to convert received chroma values.

Abstract: Systems and methods for designing data structures are provided. In one embodiment, an asynchronous first-in-first-out (FIFO) data structure may include, for example, a FIFO memory having a depth d in which d is an integer and a code generator coupled to the FIFO memory. The code generator may provide, for example, a first code sequence of length 2d. The first code sequence may have a circular property and a Hamming length of one for any two consecutive codes of the first code sequence. The first code sequence may be generated from a second code sequence by removing one or more pairs of mirrored codes of the second code sequence.

Abstract: Flesh-tones corrections may be performed to correct color shifts that may occur in transmitted video frames wherein chroma information corresponding to flesh-tone video pixels may be distorted. A target region may be determined based on a determined flesh-tones region within a spatial representation of chroma in video color space, such as Y?CrCb. The flesh-tones correction may utilize one or more methodologies based on an elliptical shape and/or a triangular shape algorithm(s). A video processing system may be utilized to analyze chroma information of received video pixels and/or to perform flesh-tones corrections by shifting the chroma value of received video pixels towards good flesh-tones regions to compensate for possible distortions. The video processing system may perform conversion calculation and/or shift operations dynamically. The video processing system may also utilize lookup tables (LUTs) to convert received chroma values.

Abstract: A method and system for processing video data using multi-pixel scaling in a memory system are provided. The multi-pixel scaling may include reading pixel data for one or more data streams from the memory system into one or more scalers, wherein each of the plurality of data streams includes a plurality of pixels, scaling the pixel via the one or more scalers and outputting the scaled pixels from the one or more scalers. Pixel data may be sequential or parallel. The plurality of scalers may be in parallel, scaling sequential pixel data with independent phase control, or scaling parallel pixel data in substantially equal phase. Pixel data may be transposed, replicated, distributed and aligned prior to reading by scalers, and may be aligned merged and transposed after scaling. Scaling may include interpolation or sub sampling using pixel phase, position, step size and scaler quantities.

Abstract: Presented herein is a scheme for reducing the likelihood of erroneous DQS signals. Logic is incorporated proximate to a memory controller and receives a signal indicating a read request and a DQS signal from a memory module. The logic transmits a signal indicating the presence of data, based on the timing relationship between the DQS signals and signal indicating read requests.

Abstract: Methods of setting numerically controlled delay lines using step sizes based on a delay locked loop lock value are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: calculating an offset value for at least one NCDL; and interpolating a new offset value for the at least one NCDL, based on a change in a delay locked loop (DLL) output value from a previous DLL output value to a new DLL output value.

Abstract: A system and method for scan testing an NCDL and latches controlled by the NCDL is presented. The NCDL is controlled by control logic, a switch is used to control the latches by a clock signal that is not controlled by the control logic. A controllability circuit provides test vectors to, and controls, the NCDL. The outputs of the NCDL are observed by an observability circuit that captures the outputs of the NCDL.

Abstract: Presented herein are system(s), method(s), and apparatus for maintaining a least recently used list for a cache. In one embodiment, there is presented a circuit for storing a list of a plurality of locations for a cache line. The circuit comprises a multiplexer, a plurality of registers, and a plurality of logic circuits. The multiplexer receives an indicator indicating a cache hit or cache miss for the cache line. The multiplexer provides an output identifying the least recently used location if the indicator indicates a cache miss, and an output identifying an accessed location if the indicator indicates a cache hit. The plurality of registers store identifiers identifying particular ones of the plurality of locations. The plurality of registers comprise a most recently used register and a remaining plurality of registers. The plurality of logic circuits correspond respectively to the remaining plurality of registers and respectively control a corresponding plurality of signals.

Abstract: Systems and methods for designing data structures are provided. In one embodiment, an asynchronous first-in-first-out (FIFO) data structure may include, for example, a FIFO memory having a depth d in which d is an integer and a code generator coupled to the FIFO memory. The code generator may provide, for example, a first code sequence of length 2d. The first code sequence may have a circular property and a Hamming length of one for any two consecutive codes of the first code sequence. The first code sequence may be generated from a second code sequence by removing one or more pairs of mirrored codes of the second code sequence.

Abstract: A system and method for generating a sequence of 2D addresses, the sequence having the property of a Hamming distance of one between consecutive addresses and the circular property, where D is an arbitrary integer. A sequence of length equal to the next power of 2, from 2D, is used to determine the sequence of 2D addresses. The sequence of addresses is used in an asynchronous first-in-first-out (FIFO) data structure, which may include, for example, a FIFO memory having a depth D and a code generator coupled to the FIFO memory. The first code sequence may be generated from a second code sequence by removing one or more pairs of mirrored codes of the second code sequence.

Abstract: Methods of setting numerically controlled delay lines using step sizes based on a delay locked loop lock value are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: calculating an offset value for at least one NCDL; and interpolating a new offset value for the at least one NCDL, based on a change in a delay locked loop (DLL) output value from a previous DLL output value to a new DLL output value.

Abstract: Presented herein is a scheme for reducing the likelihood of erroneous DQS signals. Logic is incorporated proximate to a memory controller and receives a signal indicating a read request and a DQS signal from a memory module. The logic transmits a signal indicating the presence of data, based on the timing relationship between the DQS signals and signal indicating read requests.

Abstract: A system and method for scan testing an NCDL and latches controlled by the NCDL is presented herein. Wherein the NCDL is controlled by control logic, a switch is used to control the latches by a clock signal that is not controlled by the control logic. A controllability circuit provides test vectors to, and controls, the NCDL. The outputs of the NCDL are observed by an observability circuit that captures the outputs of the NCDL.