Abstract: Systems and methods of identifying errors in RF cabling using system level distance to fault. A method of determining system level RF health in an RF deployment, the method including predicting an RF health of the deployment based on a known attribute of the deployment; receiving a distance to fault (DTF) measurement from the deployment, wherein receiving the DTF measurement includes: transmitting a test signal into a cable associated with the RF deployment; and receiving a return signal from the cable, the return signal including a reflection; comparing the predicted RF health to the received DTF measurement; and identifying mismatches between the predicted RF health and the received DTF measurement based on the comparing.

Abstract: A system for measurement is provided. The system includes a first optical path configured to supply first light pulses with a first range of wavelengths; a second optical path configured to supply second light pulses with a second range of wavelengths shorter than the first range of wavelengths; an optical I/O unit configured to emit the first light pulses and the second light pulses to a target and acquire a light from the target to detect CARS light pluses from the target by a detector; and a first phase modulating unit configured to vary phase differences between the first light pulses and the second light pulses as the first light pulses and the second light pulses are emitted via the optical I/O unit.

Abstract: A device of detecting a current from a sensor is disclosed. The device includes an integrating circuit including a network of capacitors for providing a gain setting and configured to convert the current to a voltage ramp over a length of integration time, the integrating circuit further including a reset switch configured to connect an input and an output of the network of capacitors; an ADC configured to digitize the voltage ramp into a plurality of voltage samples; and a set of modules including an analyzing module configured to analyze the plurality of voltage samples to determine a slope of the voltage ramp; an outputting module configured to determine a magnitude of the current based on the slope of the voltage ramp and the gain setting; and a reconfiguring module that is configured to reconfigure the network of capacitors and reset the voltage ramp via the reset switch.

Abstract: A system for measurement is provided. The system includes a first optical path configured to supply first light pulses with a first range of wavelengths; a second optical path configured to supply second light pulses with a second range of wavelengths shorter than the first range of wavelengths; an optical I/O unit configured to emit the first light pulses and the second light pulses to a target and acquire a light from the target to detect CARS light pluses from the target by a detector; and a first phase modulating unit configured to vary phase differences between the first light pulses and the second light pulses as the first light pulses and the second light pulses are emitted via the optical I/O unit.

Abstract: A device of detecting a current from a sensor is disclosed. The device includes an integrating circuit including a network of capacitors for providing a gain setting and configured to convert the current to a voltage ramp over a length of integration time, the integrating circuit further including a reset switch configured to connect an input and an output of the network of capacitors; an ADC configured to digitize the voltage ramp into a plurality of voltage samples; and a set of modules including an analyzing module configured to analyze the plurality of voltage samples to determine a slope of the voltage ramp; an outputting module configured to determine a magnitude of the current based on the slope of the voltage ramp and the gain setting; and a reconfiguring module that is configured to reconfigure the network of capacitors and reset the voltage ramp via the reset switch.

Abstract: A device of detecting a current from a sensor is disclosed. The device includes an integrating circuit including a network of capacitors for providing a gain setting and configured to convert the current to a voltage ramp over a length of integration time, the integrating circuit further including a reset switch configured to connect an input and an output of the network of capacitors; an ADC configured to digitize the voltage ramp into a plurality of voltage samples; and a set of modules including an analyzing module configured to analyze the plurality of voltage samples to determine a slope of the voltage ramp; an outputting module configured to determine a magnitude of the current based on the slope of the voltage ramp and the gain setting; and a reconfiguring module that is configured to reconfigure the network of capacitors and reset the voltage ramp via the reset switch.

Abstract: A device of detecting a current from a sensor is disclosed. The device includes an integrating circuit including a network of capacitors for providing a gain setting and configured to convert the current to a voltage ramp over a length of integration time, the integrating circuit further including a reset switch configured to connect an input and an output of the network of capacitors; an ADC configured to digitize the voltage ramp into a plurality of voltage samples; and a set of modules including an analyzing module configured to analyze the plurality of voltage samples to determine a slope of the voltage ramp; an outputting module configured to determine a magnitude of the current based on the slope of the voltage ramp and the gain setting; and a reconfiguring module that is configured to reconfigure the network of capacitors and reset the voltage ramp via the reset switch.

Abstract: The present application generally relates to systems and methods for managing a displayless portable electronic device comprising at least one memory operable to store a plurality of media files, the plurality of media files being organized into a plurality of media groups; at least one wireless communication antenna operable to communicate with one or more computing devices, each of the one or more computing devices comprising a display and executing a media service application; and a processor communicatively coupled with the at least one memory and the at least one wireless communication antenna.

Abstract: Methods and circuits for detecting an ion current in a mass spectrometer are described. A circuit and a method may involve converting, over a length of integration time, the ion current to a voltage ramp by an integrating circuit having a gain setting. The circuit and the method may also involve determining a slope of the voltage ramp. The circuit and the method may also involve determining a magnitude of the ion current based on the slope of the voltage ramp and the gain setting. The circuit and the method may further involves determining an out-of-range state based on the voltage ramp and adjusting the gain setting of the integrating circuit, or the length of integration time or both, in response to the determining of the out-of-range state.

Abstract: Methods and circuits for detecting an ion current in a mass spectrometer are described. A circuit and a method may involve converting, over a length of integration time, the ion current to a voltage ramp by an integrating circuit having a gain setting. The circuit and the method may also involve determining a slope of the voltage ramp. The circuit and the method may also involve determining a magnitude of the ion current based on the slope of the voltage ramp and the gain setting. The circuit and the method may further involves determining an out-of-range state based on the voltage ramp and adjusting the gain setting of the integrating circuit, or the length of integration time or both, in response to the determining of the out-of-range state.

Abstract: The present application generally relates to systems and methods for managing a displayless portable electronic device comprising at least one memory operable to store a plurality of media files, the plurality of media files being organized into a plurality of media groups; at least one wireless communication antenna operable to communicate with one or more computing devices, each of the one or more computing devices comprising a display and executing a media service application; and a processor communicatively coupled with the at least one memory and the at least one wireless communication antenna.

Abstract: Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Abstract: Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed.

Abstract: Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Abstract: Systems and methods are disclosed to automatically design a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture with programmable processor and one or more co-processors for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.

Abstract: Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Abstract: Systems and methods are disclosed to automatically determine an optimal number format representation for a model or code to be implemented in a custom integrated circuit (IC) by determining a ratio of dynamic range to static range in the model or code, and selecting a floating point or a fixed point number representation based on the ratio; determining the optimal number representation format based on a cost function that includes hardware area and power cost associated with a predetermined bit precision arithmetic; automatically generating a processor architecture customized to the optimal number representation format; and synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Abstract: Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed.

Abstract: Systems and methods are disclosed to automatically design a custom integrated circuit includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically devising a processor architecture and generating a processor chip specification uniquely customized to the computer readable code which satisfies the constraints; and synthesizing the chip specification into a layout of the custom integrated circuit.

Abstract: Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.