Patents by Inventor Anand Sadashiv Date

Anand Sadashiv Date has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and structure for source synchronous circuit in a system synchronous platform
    Patent number: 8497704
    Abstract: Methods and circuits in an application circuit to compensate for skew in the transmission of serial data between field programmable gate arrays (FPGAs) in the application circuit. A clock signal source external to both FPGAs generates a clock signal applied to both FPGAs. A transmitting FPGA generates a serial data stream comprising the current values of a plurality of signals within the transmitting FPGA and transmits the serial data stream based on its clock signal. The receiving FPGA receives the serial data stream and applies a programmed delay to the received serial data stream to compensate for skew in received serial data stream relative to its clock signal. The programmed delay value may be determined at initialization (or reset) of the FPGAs by transmitting synchronization data from the first transmitting FPGA to the receiving FPGA. The receiving FPGA adjusts a programmable delay while receiving synchronization data until it sense bit and word alignment relative to its clock signal.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: July 30, 2013
    Assignee: LSI Corporation
    Inventors: Devendra Bahadur Singh, Anand Sadashiv Date, Hrishikesh Suresh Sabnis
  • METHODS AND STRUCTURE FOR SOURCE SYNCHRONOUS CIRCUIT IN A SYSTEM SYNCHRONOUS PLATFORM
    Publication number: 20130021059
    Abstract: Methods and circuits in an application circuit to compensate for skew in the transmission of serial data between field programmable gate arrays (FPGAs) in the application circuit. A clock signal source external to both FPGAs generates a clock signal applied to both FPGAs. A transmitting FPGA generates a serial data stream comprising the current values of a plurality of signals within the transmitting FPGA and transmits the serial data stream based on its clock signal. The receiving FPGA receives the serial data stream and applies a programmed delay to the received serial data stream to compensate for skew in received serial data stream relative to its clock signal. The programmed delay value may be determined at initialization (or reset) of the FPGAs by transmitting synchronization data from the first transmitting FPGA to the receiving FPGA. The receiving FPGA adjusts a programmable delay while receiving synchronization data until it sense bit and word alignment relative to its clock signal.
    Type: Application
    Filed: July 18, 2011
    Publication date: January 24, 2013
    Applicant: LSI CORPORATION
    Inventors: Devendra Bahadur Singh, Anand Sadashiv Date, Hrishikesh Suresh Sabnis