Abstract: An integrated circuit may include a plurality of input/output (I/O) cells used for communicating signals, power, and ground to and from a core of the integrated circuit. The I/O cells may each include a bond pad formed in one or more top metal layers. One or more of the bond pads may be offset a predetermined distance from an I/O cell edge corresponding to a chip edge of the integrated circuit. A volume may be determined by the I/O cell edge and the predetermined distance and one or more rails may be disposed in the volume and in at least one metal layer common with at least one metal layer of the bond pad. The rails may be involved in the discharge of electrostatic discharge (ESD) current, and may reduce path resistance of the path used to discharge the ESD current.

Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.

Abstract: A circuit may receive control signals to generate an output signal with pulses corresponding to pulses of a source signal. The circuit may include a primary circuit and an auxiliary circuit. The primary circuit may constantly participate in the generation of pulses of the output signal. The auxiliary circuit may selectively participate with the primary circuit in the generation of the pulses. For two consecutive pulses of the output signal, whether the auxiliary circuit participates in generating the latter of the two pulses may depend on whether a threshold level is crossed during generation of the consecutive pulses.

Abstract: A design flow of an integrated circuit may include a skeleton input/output (I/O) generation stage during which information about ESD protection circuitry and rails but not functional circuitry of the I/O cells of the integrated circuit is generated. The information may be used in an ESD analysis stage to generate performance characteristics of the ESD protection circuitry. Results of the ESD analysis may then be used to design optimized ESD protection circuitry along with the rest of the circuit components of the I/O cells. In this way, the design of ESD protection circuitry may be optimized without having to redo a completed I/O cell design and significantly delay the design flow before tapeout.

Abstract: An automated system for tracking inventory is provided. The automated system tracks the sufficiency of an inventory by the weight of the items composing the inventory so that resulting inventory deficiencies can be automatically sensed either continuously or periodically at predetermined polling intervals through container transducers coupled to a WIFI enabled microprocessor, wherein the microprocessor posts the weight-based output of the transducers to a cloud server that determines if the weight-based output signifies an inventory deficiency by comparing it to a predetermined threshold. A user may through their computer set the predetermined threshold and polling intervals. The user may also export the cloud server determinations in the form of alerts back to their computer or to registered user-suppliers for replenishing the deficient inventory.

Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.

Abstract: Topological insulators can be utilized in a new type of infrared photodetector that is intrinsically sensitive to the polarization of incident light and static magnetic fields. The detector isolates single topological insulator surfaces and allows light collection and exposure to static magnetic fields. The wavelength range of interest is between 750 nm and about 100 microns. This detector eliminates the need for external polarization selective optics. Polarization sensitive infrared photodetectors are useful for optoelectronics applications, such as light detection in environments with low visibility in the visible wavelength regime.

Abstract: A design flow of an integrated circuit may include a skeleton input/output (I/O) generation stage during which information about ESD protection circuitry and rails but not functional circuitry of the I/O cells of the integrated circuit is generated. The information may be used in an ESD analysis stage to generate performance characteristics of the ESD protection circuitry. Results of the ESD analysis may then be used to design optimized ESD protection circuitry along with the rest of the circuit components of the I/O cells. In this way, the design of ESD protection circuitry may be optimized without having to redo a completed I/O cell design and significantly delay the design flow before tapeout.

Abstract: Ion implantation or deposition can be used to modify the bulk electrical properties of topological insulators. More particularly, ion implantation or deposition can be used to compensate for the non-zero bulk conductivity due to extrinsic charge carriers. The direct implantation of deposition/annealing of dopants allows better control over carrier concentrations for the purposes of achieving low bulk conductivity. Ion implantation or deposition enables the fabrication of inhomogeneously doped structures, enabling new types of device designs.

Abstract: An integrated circuit may include a plurality of input/output (I/O) cells used for communicating signals, power, and ground to and from a core of the integrated circuit. The I/O cells may each include a bond pad formed in one or more top metal layers. One or more of the bond pads may be offset a predetermined distance from an I/O cell edge corresponding to a chip edge of the integrated circuit. A volume may be determined by the I/O cell edge and the predetermined distance and one or more rails may be disposed in the volume and in at least one metal layer common with at least one metal layer of the bond pad. The rails may be involved in the discharge of electrostatic discharge (ESD) current, and may reduce path resistance of the path used to discharge the ESD current.

Abstract: The present disclosure relates to systems and methods for managing documents such as a prior art documents and documents for submission to government agencies such as an information disclosure statement (IDS) configured for submission to a patent office. In certain aspects, the system and methods include automatic retrieval of relevant documents, for example using a crawler service over a network such as the Internet. In certain aspects, the systems and methods include automatic optical character recognition and template matching to facilitate the extraction of information relating to certain documents. In certain aspects, the system and methods include a generating interface configured to present information to a generating user and to allow the generating user to select options relating to the citation of references in a particular patent family.

Abstract: Ion implantation or deposition can be used to modify the bulk electrical properties of topological insulators. More particularly, ion implantation or deposition can be used to compensate for the non-zero bulk conductivity due to extrinsic charge carriers. The direct implantation of deposition/annealing of dopants allows better control over carrier concentrations for the purposes of achieving low bulk conductivity. Ion implantation or deposition enables the fabrication of inhomogeneously doped structures, enabling new types of device designs.

Abstract: A transition tracking circuit may be configured to receive a first input signal and a second input signal from a level shifter. The transition tracking circuit may be configured to track earlier falling transitions of the first and second signals to generate an output signal.

Abstract: The present invention provides a forecasting engine with the ability to minimize prediction error in a preferred direction. It comprises of a receiver configured to receive training data samples. In addition, the forecasting engine includes a building module configured to build a base learner model from the training data samples. In addition, the forecasting engine includes a custom error function that emphasizes prediction error along a pre-configured direction. In addition, the forecasting engine includes an error determination module configured to determine the prediction error made by the base learner model. In addition, the forecasting engine includes an error minimization module configured to construct a new model that has lesser prediction error than the base learner model, where prediction error is as defined by the custom error function.