Patents by Inventor Anand T. Krishnan
Anand T. Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140024144Abstract: Integrated circuit dies and methods of making dies are disclosed. An embodiment of a die includes at least one transistor gate, wherein the gate has an area. A conductor is connected to the gate, and wherein the conductor has an area. The area of the conductor is proportional to the area of the gate raised to a power, wherein the power is a function of the failure rate of the gate.Type: ApplicationFiled: September 27, 2013Publication date: January 23, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Palkesh Jain, Anand T. Krishnan
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Publication number: 20130161718Abstract: Integrated circuit dies and methods of making dies are disclosed. An embodiment of a die includes at least one transistor gate, wherein the gate has an area. A conductor is connected to the gate, and wherein the conductor has an area. The area of the conductor is proportional to the area of the gate raised to a power, wherein the power is a function of the failure rate of the gate.Type: ApplicationFiled: June 25, 2012Publication date: June 27, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Palkesh Jain, Anand T. Krishnan
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Patent number: 7737717Abstract: A method for evaluating gate dielectrics (100) includes providing a test structure (101). The test structure includes a gate stack that includes a gate electrode on a gate dielectric on a substrate, and at least one diffusion region diffused in the substrate including a portion below the gate stack and a portion beyond the gate stack. Pre-stress off-state I-V testing (102) is performed on the test structure to obtain pre-stress I-V test data, wherein the pre-stress off-state I-V testing includes a first measurement involving the gate electrode, the substrate and the diffusion region, a second measurement involving the gate electrode and the substrate with the diffusion region floating, and a third measurement involving the gate electrode and the diffusion region with the substrate floating. The test structure is then stressed (103) including electrically stressing for a time (t).Type: GrantFiled: September 12, 2008Date of Patent: June 15, 2010Assignee: Texas Instruments IncorporatedInventors: Paul Edward Nicollian, Anand T. Krishnan, Vijay K. Reddy
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Patent number: 7638412Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.Type: GrantFiled: July 24, 2007Date of Patent: December 29, 2009Assignee: Texas Instruments IncorporatedInventors: James D. Gallia, Srikanth Krishnan, Anand T. Krishnan
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Publication number: 20090224795Abstract: A method for evaluating gate dielectrics (100) includes providing a test structure (101). The test structure includes a gate stack that includes a gate electrode on a gate dielectric on a substrate, and at least one diffusion region diffused in the substrate including a portion below the gate stack and a portion beyond the gate stack. Pre-stress off-state I-V testing (102) is performed on the test structure to obtain pre-stress I-V test data, wherein the pre-stress off-state I-V testing includes a first measurement involving the gate electrode, the substrate and the diffusion region, a second measurement involving the gate electrode and the substrate with the diffusion region floating, and a third measurement involving the gate electrode and the diffusion region with the substrate floating. The test structure is then stressed (103) including electrically stressing for a time (t).Type: ApplicationFiled: September 12, 2008Publication date: September 10, 2009Inventors: Paul Edward Nicollian, Anand T. Krishnan, Vijay K. Reddy
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Patent number: 7450452Abstract: A method of manufacturing a semiconductor device includes providing an electrical connection to a well of a MOS transistor of a static random access memory (SRAM) cell. A predetermined voltage is applied to the well using the connection to cause a threshold voltage (Vt) of said transistor to change. The change is employed to identify a reliability characteristic of the semiconductor device. An SRAM parameter is altered to modify the reliability characteristic.Type: GrantFiled: June 22, 2007Date of Patent: November 11, 2008Assignee: Texas Instruments IncorporatedInventors: Juan A. Rosal, Michael Allen Ball, Jayesh C. Raval, Anand T. Krishnan
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Publication number: 20070297254Abstract: A method of manufacturing a semiconductor device includes providing an electrical connection to a well of a MOS transistor of a static random access memory (SRAM) cell. A predetermined voltage is applied to the well using the connection to cause a threshold voltage (Vt) of said transistor to change. The change is employed to identify a reliability characteristic of the semiconductor device. An SRAM parameter is altered to modify the reliability characteristic.Type: ApplicationFiled: June 22, 2007Publication date: December 27, 2007Applicant: Texas Instruments IncorporatedInventors: Juan A. Rosal, Michael Allen Ball, Jayesh C. Raval, Anand T. Krishnan
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Patent number: 7262468Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.Type: GrantFiled: December 28, 2001Date of Patent: August 28, 2007Assignee: Texas Instruments IncorporatedInventors: James D. Gallia, Srikanth Krishnan, Anand T. Krishnan
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Patent number: 7218132Abstract: Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.Type: GrantFiled: November 30, 2005Date of Patent: May 15, 2007Assignee: Texas Instruments IncorporatedInventors: Anand T. Krishnan, Srikanth Krishnan, Vijay Reddy, Cathy Chancellor
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Patent number: 7212023Abstract: Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.Type: GrantFiled: September 7, 2004Date of Patent: May 1, 2007Assignee: Texas Instruments IncorporatedInventors: Anand T. Krishnan, Srikanth Krishnan, Vijay Reddy, Cathy Chancellor
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Patent number: 7208380Abstract: The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a stress inducing pattern on a backside of a microelectronics wafer and growing a gate oxide layer on a front side of the microelectronics wafer in the presence of a tensile stress caused by the stress inducing pattern.Type: GrantFiled: March 18, 2005Date of Patent: April 24, 2007Assignee: Texas Instruments IncorporatedInventors: Anand T. Krishnan, Srinivasan Chakravarthi, Haowen Bu
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Patent number: 7071092Abstract: An embodiment of the invention is an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5. Another embodiment of the invention is a method of manufacturing an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5.Type: GrantFiled: January 25, 2005Date of Patent: July 4, 2006Assignee: Texas Instruments IncorporatedInventors: Anand T. Krishnan, Srikanth Krishnan
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Patent number: 6969902Abstract: An embodiment of the invention is an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5. Another embodiment of the invention is a method of manufacturing an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5.Type: GrantFiled: March 21, 2003Date of Patent: November 29, 2005Assignee: Texas Instruments IncorporatedInventors: Anand T. Krishnan, Srikanth Krishnan
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Publication number: 20040183102Abstract: An embodiment of the invention is an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5. Another embodiment of the invention is a method of manufacturing an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5.Type: ApplicationFiled: March 21, 2003Publication date: September 23, 2004Inventors: Anand T. Krishnan, Srikanth Krishnan
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Patent number: 6709932Abstract: One aspect of the invention relates to a method of manufacturing a multi-gate integrated circuit device. According to the method, a protective coating substantially prevents processes used to form a second gate dielectric from affecting a first gate dielectric. In an exemplary process, an oxide gate dielectric is grown for peripheral region transistors, a protective coating of silicon nitride is deposited over the peripheral region gate oxide, the oxide and protective coating are etched from a core region, and then a second oxide dielectric is grown for core region transistors while the silicon nitride coating substantially prevents further oxide growth in the peripheral region. The protective coating can also prevent nitridation of the core region gate dielectric from affecting the peripheral region gate dielectric.Type: GrantFiled: August 30, 2002Date of Patent: March 23, 2004Assignee: Texas Instruments IncorporatedInventors: Anand T. Krishnan, Vijay Reddy
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Publication number: 20040043567Abstract: One aspect of the invention relates to a method of manufacturing a multi-gate integrated circuit device. According to the method, a protective coating substantially prevents processes used to form a second gate dielectric from affecting a first gate dielectric. In an exemplary process, an oxide gate dielectric is grown for peripheral region transistors, a protective coating of silicon nitride is deposited over the peripheral region gate oxide, the oxide and protective coating are etched from a core region, and then a second oxide dielectric is grown for core region transistors while the silicon nitride coating substantially prevents further oxide growth in the peripheral region. The protective coating can also prevent nitridation of the core region gate dielectric from affecting the peripheral region gate dielectric.Type: ApplicationFiled: August 30, 2002Publication date: March 4, 2004Inventors: Anand T. Krishnan, Vijay Reddy
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Publication number: 20030122190Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.Type: ApplicationFiled: December 28, 2001Publication date: July 3, 2003Applicant: Texas Instruments IncorporatedInventors: James D. Gallia, Srikanth Krishnan, Anand T. Krishnan