Patents by Inventor Anand V. Kamannavar

Anand V. Kamannavar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7447966
    Abstract: Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification command to verify a portion of a hardware design of a device under test. The error verification object is compiled in accordance with data provided by an error scripting module. The error scripting module has access to hardware-specific data corresponding to the hardware design of the device under test. The compiled object is sent to the device under test and a response to the compiled object is received from the device under test. The received response from the device under test is parsed in accordance with data provided by the error scripting module.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: November 4, 2008
    Assignee: Hewlett-Packard Development Company
    Inventors: Anand V. Kamannavar, Nathan Dirk Zelle, Bradley Forrest Bass, Sahir Shiraz Hoda, Erich Matthew Gens
  • Patent number: 7401269
    Abstract: In one embodiment, the present invention is directed to a method for inserting errors into data to facilitate validation of an error detection algorithm. The method comprises: receiving a data corruption command for a plurality of bits; determining, from the data corruption command, a plurality of bit fields within the plurality of bits for data corruption; determining a minimum and maximum number of errors for each of the plurality of bit fields; determining a total number of errors to be inserted; inserting the minimum number of errors into each of the plurality of bit fields at random locations; and randomly inserting additional errors into the plurality of bit fields subject to the maximum number of errors until the total number of errors are inserted.
    Type: Grant
    Filed: May 10, 2003
    Date of Patent: July 15, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Sahir S. Hoda, Brad F. Bass, Nathan D. Zelle, Anand V. Kamannavar
  • Publication number: 20040225932
    Abstract: In one embodiment, the present invention is directed to a method for inserting errors into data to facilitate validation of an error detection algorithm. The method comprises: receiving a data corruption command for a plurality of bits; determining, from the data corruption command, a plurality of bit fields within the plurality of bits for data corruption; determining a minimum and maximum number of errors for each of the plurality of bit fields; determining a total number of errors to be inserted; inserting the minimum number of errors into each of the plurality of bit fields at random locations; and randomly inserting additional errors into the plurality of bit fields subject to the maximum number of errors until the total number of errors are inserted.
    Type: Application
    Filed: May 10, 2003
    Publication date: November 11, 2004
    Inventors: Sahir S. Hoda, Brad F. Bass, Nathan D. Zelle, Anand V. Kamannavar