Patents by Inventor Anand Venkat

Anand Venkat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11954466
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that perform machine learning-guided compiler optimizations for register-based hardware architectures. Examples disclosed herein include a non-transitory computer readable medium comprising instructions that, when executed, cause a machine to at least select a register-based compiler transformation to apply to source code at a current position in a search tree, determine whether the search tree is in need of pruning based on an output of a query to a machine learning (ML) model, in response to determining the search tree is in need of pruning, prune the search tree at the current position, in response to applying the selected register-based compiler transformation to the source code, generate a code variant, calculate a score associated with the source code at the current position in the search tree, and update parameters of the machine learning (ML) model to include the calculated score.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Anand Venkat, Justin Gottschlich, Niranjan Hasabnis
  • Patent number: 11733981
    Abstract: An example apparatus comprises a transformation generator to generate a population of code variants corresponding to an input code, the population of code variants to include transformation sequences of the input code, a dependence analyzer to analyze the population of code variants for dependence vectors, a profile controller to profile the population of code variants to determine performance metrics of hardware during an execution of respective ones of the transformation sequences, and a hash code generator to generate hash codes for storing in a database, the hash codes (a) corresponding to a combination of the dependence vectors and respective performance metrics and (b) mapped to respective transformation sequences.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Anand Venkat, Justin Gottschlich, Shengtian Zhou, Vasileios Porpodas
  • Publication number: 20220121430
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that perform machine learning-guided compiler optimizations for register-based hardware architectures. Examples disclosed herein include a non-transitory computer readable medium comprising instructions that, when executed, cause a machine to at least select a register-based compiler transformation to apply to source code at a current position in a search tree, determine whether the search tree is in need of pruning based on an output of a query to a machine learning (ML) model, in response to determining the search tree is in need of pruning, prune the search tree at the current position, in response to applying the selected register-based compiler transformation to the source code, generate a code variant, calculate a score associated with the source code at the current position in the search tree, and update parameters of the machine learning (ML) model to include the calculated score.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 21, 2022
    Inventors: Anand Venkat, Justin Gottschlich, Niranjan Hasabnis
  • Publication number: 20220091895
    Abstract: Methods, apparatus, systems, and articles of manufacture to determine execution cost are disclosed. An example apparatus includes memory; instructions included in the apparatus; and processor circuitry to execute the instruction to: cause a plurality of instructions corresponding to a mnemonic to be executed; determine an average execution cost of the plurality of instructions; determine a standard deviation of execution costs of the plurality of instructions; and generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.
    Type: Application
    Filed: December 2, 2021
    Publication date: March 24, 2022
    Inventors: Niranjan Hasabnis, Justin Gottschlich, Jesmin Jahan Tithi, Anand Venkat
  • Publication number: 20210103434
    Abstract: An example apparatus comprises a transformation generator to generate a population of code variants corresponding to an input code, the population of code variants to include transformation sequences of the input code, a dependence analyzer to analyze the population of code variants for dependence vectors, a profile controller to profile the population of code variants to determine performance metrics of hardware during an execution of respective ones of the transformation sequences, and a hash code generator to generate hash codes for storing in a database, the hash codes (a) corresponding to a combination of the dependence vectors and respective performance metrics and (b) mapped to respective transformation sequences.
    Type: Application
    Filed: November 24, 2020
    Publication date: April 8, 2021
    Inventors: Anand Venkat, Justin Gottschlich, Shengtian Zhou, Vasileios Porpodas