Patents by Inventor Ananda C. S. Mahesh

Ananda C. S. Mahesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220172325
    Abstract: A system that executes a distributed application, such as a machine learning model, can have a processor node among a system of nodes to generate a request for data and a storage node among a system of nodes that stores the requested data. The processor node will use the data for iterative processing to train a machine learning model. The storage node receives the request for the data, reads the data, preprocess the data to perform requested data transformation on the data on demand, and provides the preprocessed data to the processor node for the iterative processing. The processor node can request storage system nodes to store data in a manner suitable for preprocessing. In response to receiving a request, the storage node can interpret hints or metadata associated with the storage operation and perform the requested data store operation.
    Type: Application
    Filed: February 16, 2022
    Publication date: June 2, 2022
    Inventor: Ananda C. S. MAHESH
  • Patent number: 11055189
    Abstract: The present disclosure includes apparatuses comprising replaceable memory. An example apparatus may include a controller and a memory package coupled to the controller and including a plurality of memory dies. At least one of the memory package and the controller may be a replaceable unit that is removable from the apparatus and replaceable with a different replaceable unit while maintaining operation of the apparatus.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ananda C. S. Mahesh, Gregory P. Shogan
  • Publication number: 20210117320
    Abstract: Disclosed embodiments relate to constructing an allocation of memory in a memory subsystem. In one example, a method includes receiving from a host system among a pool of host systems, a request to construct an allocation of memory, the pool of host systems being coupled to a pool of memory devices, selecting multiple memory devices among the pool of memory devices, selecting multiple memory components among the multiple memory devices, aggregating the multiple memory components to implement the allocation of memory, and providing, to the host system, hierarchical addresses to be used to access the multiple memory components implementing the allocation of memory, the hierarchical addresses each including a device ID of an associated memory device and a host ID of an associated host system.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 22, 2021
    Inventor: Ananda C. S. Mahesh
  • Publication number: 20210117117
    Abstract: Disclosed embodiments relate to constructing an allocation of memory in a memory subsystem using heterogeneous memory components. In one example, a method includes receiving, from a host system, a request to construct an allocation of memory, selecting multiple memory devices from a pool of memory devices, selecting multiple memory components among the multiple memory devices, aggregating the multiple memory components to implement the allocation of memory, and providing, to the host system, hierarchical addresses to be used to access the multiple memory components implementing the allocation of memory, the hierarchical addresses each including a device ID of an associated memory device.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 22, 2021
    Inventor: Ananda C. S. Mahesh
  • Publication number: 20200042414
    Abstract: The present disclosure includes apparatuses comprising replaceable memory. An example apparatus may include a controller and a memory package coupled to the controller and including a plurality of memory dies. At least one of the memory package and the controller may be a replaceable unit that is removable from the apparatus and replaceable with a different replaceable unit while maintaining operation of the apparatus.
    Type: Application
    Filed: October 15, 2019
    Publication date: February 6, 2020
    Inventors: Ananda C. S. Mahesh, Gregory P. Shogan
  • Patent number: 10489257
    Abstract: The present disclosure includes apparatuses comprising replaceable memory. An example apparatus may include a controller and a memory package coupled to the controller and including a plurality of memory dies. At least one of the memory package and the controller may be a replaceable unit that is removable from the apparatus and replaceable with a different replaceable unit while maintaining operation of the apparatus.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ananda C. S. Mahesh, Gregory P. Shogan
  • Publication number: 20190050305
    Abstract: The present disclosure includes apparatuses comprising replaceable memory. An example apparatus may include a controller and a memory package coupled to the controller and including a plurality of memory dies. At least one of the memory package and the controller may be a replaceable unit that is removable from the apparatus and replaceable with a different replaceable unit while maintaining operation of the apparatus.
    Type: Application
    Filed: August 8, 2017
    Publication date: February 14, 2019
    Inventors: Ananda C. S. Mahesh, Gregory P. Shogan