Abstract: Some embodiments relate generally to memory arrays having complementary bitlines. With some implementations, charge sharing to facilitate midrail read operations may be incorporated therein.

Abstract: Various embodiments provide apparatuses, systems, and methods for a register file array with a plurality of sets of memory cells, wherein individual sets of memory cells of the plurality of sets of memory cells are coupled to a respective local bit line (LBL). A merge circuitry may include a multiplexer with inputs coupled to the respective LBLs, wherein the multiplexer is to couple a selected one of the LBLs to a LBL merge node. Read circuitry may be coupled to the LBL merge node to read data from a first memory cell via the selected LBL. In some embodiments, the LBL may be precharged to a supply voltage (e.g., Vcc) minus a threshold voltage, Vt, of the multiplexer transistor, as opposed to being precharged to Vcc as in prior techniques. Other embodiments may be described and claimed.

Abstract: Provided is a novel keeper circuit with a pull-up device whose strength changes for different operating supply levels so that the pull-up device is weaker for smaller supply levels and stringer for higher supply levels.

Abstract: Provided is a novel keeper circuit with a pull-up device whose strength changes for different operating supply levels so that the pull-up device is weaker for smaller supply levels and stringer for higher supply levels.