Patents by Inventor Anant Agarwal

Anant Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190026352
    Abstract: Disclosed herein are system, method, and computer program product embodiments for replication of database. In one embodiment, one or more data pages generated from a transaction are obtained at a first node. The one or more data pages are compressed. The compressed data pages are added into a first queue in a memory of the first node. The first queue includes a plurality of blocks. A first block of the compressed data pages in the first queue is transmitted to a second node when the first block of the compressed data pages becomes available for replication. The first block of the compressed data pages is stored in a persistent storage of the first node.
    Type: Application
    Filed: July 19, 2017
    Publication date: January 24, 2019
    Inventors: Nandan MARATHE, Anant Agarwal, Sagar Ranadive, Dipesh Pandit
  • Publication number: 20180365277
    Abstract: Disclosed herein are methods for retrieving data from a database. An embodiment operates searching for a key in a first index. The method determines that the searching will require a storage access request and issues the storage access request. The method continues searching for the key in a second index.
    Type: Application
    Filed: August 27, 2018
    Publication date: December 20, 2018
    Inventors: Anant Agarwal, Steven A. Kirk, Blaine French, Nandan Marathe, Shailesh Mungikar, Kaushal Mittal
  • Patent number: 10134834
    Abstract: A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: November 20, 2018
    Assignee: Cree, Inc.
    Inventors: Lin Cheng, Anant Agarwal, Vipindas Pala, John Palmour
  • Patent number: 10095543
    Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: October 9, 2018
    Assignee: Mellanox Technologies Ltd.
    Inventors: Patrick Robert Griffin, Mathew Hostetter, Anant Agarwal, Chyi-Chang Miao
  • Patent number: 10061792
    Abstract: Disclosed herein are methods for retrieving data from a database. An embodiment operates searching for a key in a first index. The method determines that the searching will require a storage access request and issues the storage access request. The method continues searching for the key in a second index.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: August 28, 2018
    Assignee: Sybase, Inc.
    Inventors: Anant Agarwal, Steven A. Kirk, Blaine French, Nandan Marathe, Shailesh Mungikar, Kaushal Mittal
  • Patent number: 10013391
    Abstract: An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a function associated with executing instructions; and reconfiguring the number of processor cores assigned to at least one of the sets during execution based on characteristics associated with executing the instructions.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: July 3, 2018
    Assignee: Massachusetts Institute of Technology
    Inventors: Anant Agarwal, David M. Wentzlaff
  • Publication number: 20180157511
    Abstract: A number of hosts in a logical cluster is adjusted up or down in an elastic manner by tracking membership of hosts in the cluster using a first data structure and tracking membership of hosts in a spare pool using a second data structure, and upon determining that a triggering condition for adding another host is met and that all hosts in the cluster are being used, selecting a host from the spare pool, and programmatically adding an identifier of the selected host to the first data structure and programmatically deleting the identifier of the selected host from the second data structure.
    Type: Application
    Filed: December 2, 2016
    Publication date: June 7, 2018
    Inventors: Manoj KRISHNAN, Anant AGARWAL, Rahul CHANDRASEKARAN, Prafulla MAHINDRAKAR, Ravi CHERUKUPALLI
  • Patent number: 9984894
    Abstract: Methods of forming a semiconductor structure include providing an insulation layer on a semiconductor layer and diffusing cesium ions into the insulation layer from a cesium ion source outside the insulation layer. A MOSFET including an insulation layer treated with cesium ions may exhibit increased inversion layer mobility.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: May 29, 2018
    Assignees: Cree, Inc., Auburn University
    Inventors: Sarit Dhar, Sei-Hyung Ryu, Anant Agarwal, John Robert Williams
  • Patent number: 9934010
    Abstract: Programming in a multiprocessor environment includes accepting a program specification that defines a plurality of processing modules and one or more channels for sending data between ports of the modules, mapping each of the processing modules to run on a set of one or more processing engines of a network of interconnected processing engines, and for at least some of the channels, assigning one or more elements of one or more processing engines in the network to the channel for sending data between respective processing modules.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: April 3, 2018
    Assignee: Mellanox Technologies Ltd.
    Inventors: Patrick Robert Griffin, Walter Lee, Anant Agarwal, David M. Wentzlaff
  • Publication number: 20180032241
    Abstract: Embodiments include an event services modeling framework. The event services modeling framework includes an event services modeling editor that provides a user interface and mechanism for users to model and customize event flow configurations within a system and/or network. The user interface can be used to connect events with actions that will take place in response to the events. The system components and/or modules that need to receive the information from the events can then react and respond appropriately. Users can modify event configurations based on their own particular needs. the event services editor can be used for generating one or more event services models. The event services models may include events, conditions (rules) for processing the events, activities to be perform during event processing, subscriber modules defined for performing the activities during event processing, and a specified time for processing the events in each modeled event flow.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 1, 2018
    Inventors: Kaushik Ghosh, Abhijit Salvi, Kevin Tully, Anant Agarwal, Alexander Chernavin, Mirza Raza, David Ragones, Sergei Ponomarev
  • Publication number: 20180032408
    Abstract: Synchronized backup and recovery of heterogeneous DBMSs is described herein. An embodiment operates by receiving, by at least one processor, a request for a data backup process at a first server; creating, by at least one processor, a pipe between processes of the first sever and the data backup process; performing, by at least one processor, the data backup process according to an execution command sent from a second server; and sending, by at least one processor, a result of the data backup process from the second server to the first server when the data backup process has terminated.
    Type: Application
    Filed: July 26, 2016
    Publication date: February 1, 2018
    Inventors: Anant AGARWAL, Mahendra Chavan, Nandan Marathe, Dipesh Pandit
  • Publication number: 20170092715
    Abstract: A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator.
    Type: Application
    Filed: December 8, 2016
    Publication date: March 30, 2017
    Inventors: Lin Cheng, Anant Agarwal, Vipindas Pala, John Palmour
  • Patent number: 9570585
    Abstract: A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: February 14, 2017
    Assignee: Cree, Inc.
    Inventors: Lin Cheng, Anant Agarwal, Vipindas Pala, John Palmour
  • Patent number: 9514050
    Abstract: A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: December 6, 2016
    Assignee: Tilera Corporation
    Inventors: Anant Agarwal, Ian Rudolf Bratt, Matthew Mattina
  • Patent number: 9478616
    Abstract: Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: October 25, 2016
    Assignee: Cree, Inc.
    Inventors: Sarit Dhar, Sei-Hyung Ryu, Lin Cheng, Anant Agarwal
  • Patent number: 9396946
    Abstract: Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: July 19, 2016
    Assignee: Cree, Inc.
    Inventors: Sarit Dhar, Lin Cheng, Sei-Hyung Ryu, Anant Agarwal, John Williams Palmour, Erik Maki, Jason Gurganus, Daniel Jenner Lichtenwalner
  • Patent number: 9361402
    Abstract: Disclosed herein are system, method, and computer program product embodiments for storing data in a database using a tiered index architecture, An embodiment operates by creating a first tier and assigning a first threshold size to the first tier. When the first tier exceed the first threshold size, the system pushes data from the first tier into a second tier.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: June 7, 2016
    Assignee: SYBASE, INC.
    Inventors: Blaine French, Shailesh Mungikar, Nandan Marathe, Anant Agarwal
  • Patent number: 9349596
    Abstract: Methods of forming a silicon carbide semiconductor device are disclosed. The methods include forming a semiconductor device at a first surface of a silicon carbide substrate having a first thickness, and mounting a carrier substrate to the first surface of the silicon carbide substrate. The carrier substrate provides mechanical support to the silicon carbide substrate. The methods further include thinning the silicon carbide substrate to a thickness less the first thickness, forming a metal layer on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate, and locally annealing the metal layer to form an ohmic contact on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate. The silicon carbide substrate is singulated to provide a singulated semiconductor device.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: May 24, 2016
    Assignee: Cree, Inc.
    Inventors: Anant Agarwal, Sei-Hyung Ryu, Matthew Donofrio
  • Patent number: 9337268
    Abstract: A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: May 10, 2016
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Craig Capell, Anant Agarwal, Sei-Hyung Ryu
  • Patent number: 9306004
    Abstract: A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: April 5, 2016
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Craig Capell, Anant Agarwal, Sei-Hyung Ryu