Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: Methods and apparatus to operate various logic blocks of an integrated circuit (IC) at independent voltages are described. In one embodiment, supply of power to one or more domains in an IC is adjusted based on an indication that power consumption by components of the corresponding domain is to be modified. Other embodiments are also described.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: A system is disclosed. The system includes a central processing unit (CPU) to operate in one or more low power sleep states, and a power converter. The power converter includes phase inductors; and one or more power switches to drive the phase inductors. The one or more power switches are deactivated during the CPU sleep state.

Abstract: A method and apparatus for current detection for microelectronic devices using source-switched sensors. An embodiment of a current detector for a microelectronic device includes a first voltage sensor and a second voltage sensor. The first voltage sensor is to measure a first voltage of the microelectronic device during a first time period and a second voltage of the microelectronic device during a second time period. The second voltage sensor is to measure the second voltage during the first time period and the first voltage during the second time period. A voltage value is equal to the sum of the first voltage measured by the first sensor plus the first voltage measured by the second sensor, minus the sum of the second voltage measured by the first sensor plus the second voltage measured by the second sensor. Other embodiments are also described and claimed.

Abstract: A voltage regulator is described for microelectronic devices using dual edge pulse width modulated control signal. In one example a first digital duty cycle value is received from a voltage controller and a pulse width modulated waveform is generated in response to the first duty cycle value, the waveform comprising a plurality of pulses with a modulated width. The waveform is applied to a voltage generator to generate a supply of power at a voltage determined by the duty cycle of the waveform. A second digital duty cycle value is received from the controller, and the leading edge of a subsequent pulse of the waveform is advanced if the second digital duty cycle value is greater than the first digital duty cycle. The trailing edge of the subsequent pulse of the waveform is advanced if the second digital duty cycle value is less than the first digital duty cycle value.

Abstract: A method and an apparatus to regulate voltage supply have been disclosed. In one embodiment, the apparatus includes a power converter block to generate an output voltage from an input voltage and a voltage regulator controller coupled to the power converter block to input at least one time-modulated signal to the power converter block, the at least one time-modulated signal having a duty cycle, the voltage regulator controller including a counter having an increment value substantially proportional to the input voltage, wherein the counter is used to adjust the duty cycle of the at least one time-modulated signal. Other embodiments have been claimed and described.

Abstract: Methods and apparatus to operate various logic blocks of an integrated circuit (IC) at independent voltages are described. In one embodiment, supply of power to one or more domains in an IC is adjusted based on an indication that power consumption by components of the corresponding domain is to be modified. Other embodiments are also described.

Abstract: Independent power control of two or more processing cores.

Abstract: A method and an apparatus to sense supply voltage have been disclosed. In one embodiment, the apparatus includes a resistor having a first end and a second end, the first end coupled to a voltage supply and a ring oscillator sensor coupled between the second end of the resistor and ground, the ring oscillator sensor having an output coupled to a computational element. Other embodiments have been claimed and described.

Abstract: A voltage regulator is described for microelectronic devices using dual edge pulse width modulated control signal. In one example a first digital duty cycle value is received from a voltage controller and a pulse width modulated waveform is generated in response to the first duty cycle value, the waveform comprising a plurality of pulses with a modulated width. The waveform is applied to a voltage generator to generate a supply of power at a voltage determined by the duty cycle of the waveform. A second digital duty cycle value is received from the controller, and the leading edge of a subsequent pulse of the waveform is advanced if the second digital duty cycle value is greater than the first digital duty cycle.

Abstract: An input/output bus for analog sensors in an integrated circuit is described. In one example, a plurality of analog sensors generate an analog output in response to a respective event on the integrated circuit. A plurality of digitizers each coupled to an analog sensor generate a digital representation of the analog output of the respective sensor, and a communications bus coupled to the plurality of digitizers communicates the digital representations to an external device.