Patents by Inventor Anant Jahagirdar

Anant Jahagirdar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stress compensation for wafer to wafer bonding
    Patent number: 11721554
    Abstract: Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: Anant Jahagirdar, Chytra Pawashe, Aaron Lilak, Myra McDonnell, Brennen Mueller, Mauro Kobrinsky
  • STRESS COMPENSATION FOR WAFER TO WAFER BONDING
    Publication number: 20200303191
    Abstract: Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 24, 2020
    Inventors: Anant JAHAGIRDAR, Chytra PAWASHE, Aaron LILAK, Myra MCDONNELL, Brennen MUELLER, Mauro KOBRINSKY
  • Methods for double patterning photoresist
    Publication number: 20090263751
    Abstract: Embodiments of methods for double patterning photoresist are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: April 22, 2008
    Publication date: October 22, 2009
    Inventors: Swaminathan Sivakumar, Anna Lio, Elliot Tan, Charles Wallace, Anant Jahagirdar