Patents by Inventor Anant K. Agarwal

Anant K. Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120122305
    Abstract: An electronic device includes a drift layer having a first conductivity type, a buffer layer having a second conductivity type, opposite the first conductivity type, on the drift layer and forming a P-N junction with the drift layer, and a junction termination extension region having the second conductivity type in the drift layer adjacent the P-N junction. The buffer layer includes a step portion that extends over a buried portion of the junction termination extension. Related methods are also disclosed.
    Type: Application
    Filed: December 28, 2011
    Publication date: May 17, 2012
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Patent number: 8124480
    Abstract: Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on the floating guard rings and a silicon carbide surface charge compensation region is provided between the floating guard rings and is adjacent the insulating layer. Methods of fabricating such edge termination are also provided.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: February 28, 2012
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Anant K. Agarwal
  • Patent number: 8119539
    Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: February 21, 2012
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
  • Patent number: 8097919
    Abstract: An electronic device includes a drift layer having a first conductivity type, a buffer layer having a second conductivity type, opposite the first conductivity type, on the drift layer and forming a P?N junction with the drift layer, and a junction termination extension region having the second conductivity type in the drift layer adjacent the P?N junction. The buffer layer includes a step portion that extends over a buried portion of the junction termination extension. Related methods are also disclosed.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: January 17, 2012
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Publication number: 20110084284
    Abstract: A transistor may include a semiconductor drift layer of a first semiconductor material and a semiconductor channel layer on the semiconductor drift layer. The semiconductor channel layer may include a second semiconductor material different than the first semiconductor material. A semiconductor interconnection layer may be electrically coupled between the semiconductor drift layer and the semiconductor channel layer, and the semiconductor interconnection layer may include a third semiconductor material different than the first and second semiconductor materials. In addition, a control electrode may be provided on the semiconductor channel layer.
    Type: Application
    Filed: October 13, 2009
    Publication date: April 14, 2011
    Inventors: Qingchun Zhang, Sei-Hyung Ryu, Anant K. Agarwal, Sarit Dhar
  • Publication number: 20110081772
    Abstract: Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on the floating guard rings and a silicon carbide surface charge compensation region is provided between the floating guard rings and is adjacent the insulating layer. Methods of fabricating such edge termination are also provided.
    Type: Application
    Filed: November 19, 2010
    Publication date: April 7, 2011
    Inventors: Sei Hyung Ryu, Anant K. Agarwal
  • Publication number: 20110012129
    Abstract: A packaged power electronic device includes a wide bandgap bipolar driver transistor having a base, a collector, and an emitter terminal, and a wide bandgap bipolar output transistor having a base, a collector, and an emitter terminal. The collector terminal of the output transistor is coupled to the collector terminal of the driver transistor, and the base terminal of the output transistor is coupled to the emitter terminal of the driver transistor to provide a Darlington pair. An area of the output transistor is at least 3 times greater than an area of the driver transistor in plan view. For example, an area ratio of the output transistor to the driver transistor may be between about 3:1 to about 5:1. Related devices and methods of fabrication are also discussed.
    Type: Application
    Filed: July 15, 2009
    Publication date: January 20, 2011
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Publication number: 20100301929
    Abstract: Semiconductor switching devices include a wide band-gap power transistor, a wide band-gap surge current transistor that coupled in parallel to the power transistor, and a wide hand-gap driver transistor that is configured to drive the surge current transistor. Substantially all of the on-state output current of the semiconductor switching device flows through the channel of the power transistor when a drain-source voltage of the power transistor is within a first voltage range, which range may correspond, for example, to the drain-source voltages expected during normal operation. In contrast, the semiconductor switching device is further configured so that in the on-state the output current flows through both the surge current transistor and the channel of the power transistor when the drain-source voltage of the power transistor is within a second, higher voltage range.
    Type: Application
    Filed: November 2, 2009
    Publication date: December 2, 2010
    Inventors: Qingchun Zhang, James Theodore Richmond, Anant K. Agarwal, Sei-Hyung Ryu
  • Patent number: 7842549
    Abstract: Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on the floating guard rings and a silicon carbide surface charge compensation region is provided between the floating guard rings and is adjacent the insulating layer. Methods of fabricating such edge termination are also provided.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: November 30, 2010
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Anant K. Agarwal
  • Patent number: 7838377
    Abstract: A bipolar junction transistor includes a collector having a first conductivity type, a drift layer having the first conductivity type on the collector, a base layer on the drift layer and having a second conductivity type opposite the first conductivity type, a lightly doped buffer layer having the first conductivity type on the base layer and forming a p-n junction with the base layer, and an emitter mesa having the first conductivity type on the buffer layer and having a sidewall. The buffer layer includes a mesa step adjacent to and spaced laterally apart from the sidewall of the emitter mesa, and a first thickness of the buffer layer beneath the emitter mesa is greater than a second thickness of the buffer layer outside the mesa step.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: November 23, 2010
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Publication number: 20100289032
    Abstract: An electronic device includes a silicon carbide layer having a first conductivity type and a main junction adjacent a surface of the silicon carbide layer, and a junction termination region at the surface of the silicon carbide layer adjacent the main junction. Charge in the junction termination region decreases with lateral distance from the main junction, and a maximum charge in the junction termination region may be less than about 2×1014 cm?2.
    Type: Application
    Filed: March 8, 2010
    Publication date: November 18, 2010
    Inventors: Qingchun Zhang, Anant K. Agarwal, Tangali S. Sudarshan, Alexander Bolotnikov
  • Publication number: 20100133549
    Abstract: A semiconductor device may include a semiconductor buffer layer having a first conductivity type and a semiconductor mesa having the first conductivity type on a surface of the buffer layer. In addition, a current shifting region having a second conductivity type may be provided adjacent a corner between the semiconductor mesa and the semiconductor buffer layer, and the first and second conductivity types may be different conductivity types. Related methods are also discussed.
    Type: Application
    Filed: July 30, 2009
    Publication date: June 3, 2010
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Patent number: 7679223
    Abstract: An electronic circuit includes a primary wide bandgap bipolar power switching device configured to supply a load current in response to a control signal applied to a control terminal thereof, and a driver device configured to generate the control signal. At least one of the primary switching device or the driver device may include an optically triggered switching device. A discrete wide bandgap semiconductor device includes a primary bipolar device stage configured to switch between a conducting state and a nonconducting state upon application of a control current, and a bipolar driver stage configured to generate the control current and to supply the control current to the primary bipolar device stage. At least one of the primary bipolar device stage and the bipolar driver stage may include an optically triggered wide bandgap switching device.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: March 16, 2010
    Assignee: Cree, Inc.
    Inventors: Anant K. Agarwal, Sumithra Krishnaswami, James T. Richmond, Jr.
  • Publication number: 20100032685
    Abstract: An electronic device includes a drift layer having a first conductivity type, a buffer layer having a second conductivity type, opposite the first conductivity type, on the drift layer and forming a P—N junction with the drift layer, and a junction termination extension region having the second conductivity type in the drift layer adjacent the P—N junction. The buffer layer includes a step portion that extends over a buried portion of the junction termination extension. Related methods are also disclosed.
    Type: Application
    Filed: August 11, 2008
    Publication date: February 11, 2010
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Publication number: 20100009545
    Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 14, 2010
    Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
  • Patent number: 7615801
    Abstract: High voltage silicon carbide (SiC) devices, for example, thyristors, are provided. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first region of SiC is provided on the first SiC layer and has the second conductivity type. A second region of SiC is provided in the first SiC layer, has the first conductivity type and is adjacent to the first region of SiC. A second SiC layer having the first conductivity type is provided on a second surface of the voltage blocking SiC substrate. A third region of SiC is provided on the second SiC layer and has the second conductivity type. A fourth region of SiC is provided in the second SiC layer, has the first conductivity type and is adjacent to the third region of SiC. First and second contacts are provided on the first and third regions of SiC, respectively. Related methods of fabricating high voltage SiC devices are also provided.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: November 10, 2009
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Jason R. Jenny, Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Hudson McDonald Hobgood
  • Publication number: 20090212301
    Abstract: Edge termination structures for semiconductor devices are provided including a plurality of spaced apart concentric floating guard rings in a semiconductor layer that at least partially surround a semiconductor junction. The spaced apart concentric floating guard rings have a highly doped portion and a lightly doped portion. Related methods of fabricating devices are also provided herein.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 27, 2009
    Inventors: Qingchun Zhang, Charlotte Jones, Anant K. Agarwal
  • Patent number: 7572741
    Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500 ° C. to about 1300 ° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: August 11, 2009
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
  • Publication number: 20090121319
    Abstract: A bipolar junction transistor includes a collector having a first conductivity type, a drift layer having the first conductivity type on the collector, a base layer on the drift layer and having a second conductivity type opposite the first conductivity type, a lightly doped buffer layer having the first conductivity type on the base layer and forming a p-n junction with the base layer, and an emitter mesa having the first conductivity type on the buffer layer and having a sidewall. The buffer layer includes a mesa step adjacent to and spaced laterally apart from the sidewall of the emitter mesa, and a first thickness of the buffer layer beneath the emitter mesa is greater than a second thickness of the buffer layer outside the mesa step.
    Type: Application
    Filed: September 9, 2008
    Publication date: May 14, 2009
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Publication number: 20090035926
    Abstract: Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on the floating guard rings and a silicon carbide surface charge compensation region is provided between the floating guard rings and is adjacent the insulating layer. Methods of fabricating such edge termination are also provided.
    Type: Application
    Filed: August 21, 2008
    Publication date: February 5, 2009
    Inventors: Sei-Hyung Ryu, Anant K. Agarwal