Patents by Inventor Anant Pratap Singh

Anant Pratap Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8402326
    Abstract: An integrated circuit device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory cell array, comprising a plurality of data multiplexers, each data multiplexer having a plurality of inputs, comprising (i) a first input to receive write data which is representative of data to be written into the memory cells of the memory cell array in response to a write operation, and (ii) a second input to receive read data which is representative of data read from memory cells of the memory cell array, and an associated output to responsively output data from one of the plurality of inputs; and syndrome generation circuitry, coupled to the multiplexer circuitry, to generate: (i) a write data syndrome vector using the write data and (ii) a read data syndrome vector using the read data.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: March 19, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Anant Pratap Singh
  • Publication number: 20120134216
    Abstract: An integrated circuit device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory cell array, comprising a plurality of data multiplexers, each data multiplexer having a plurality of inputs, comprising (i) a first input to receive write data which is representative of data to be written into the memory cells of the memory cell array in response to a write operation, and (ii) a second input to receive read data which is representative of data read from memory cells of the memory cell array, and an associated output to responsively output data from one of the plurality of inputs; and syndrome generation circuitry, coupled to the multiplexer circuitry, to generate: (i) a write data syndrome vector using the write data and (ii) a read data syndrome vector using the read data.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 31, 2012
    Applicant: Micron Technology, Inc.
    Inventor: Anant Pratap Singh
  • Patent number: 8069377
    Abstract: An integrated circuit device (for example, a logic device or a memory device (such as, a discrete memory device)), including a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, multiplexer circuitry, coupled to the memory cell array, wherein the multiplexer circuitry includes a plurality of data multiplexers, each data multiplexer having a plurality of inputs, including (i) a first input to receive write data which is representative of data to be written into the memory cells of the memory cell array in response to a write operation, and (ii) a second input to receive read data which is representative of data read from memory cells of the memory cell array, and an associated output to responsively output data from one of the plurality of inputs, and syndrome generation circuitry, coupled to the multiplexer circuitry, to generate: (i) a write data syndrome vector using the write data and (ii) a read data syndrome vector using the read data.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: November 29, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Anant Pratap Singh
  • Patent number: 7499352
    Abstract: An integrated circuit device (for example, a logic device (such as, a microcontroller or microprocessor) or a portion of a memory device (such as, a discrete memory)), including (a) a memory cell array having a plurality of memory cells arranged in (i) a plurality of normal rows of memory cells which are associated with and selectable via normal row addresses and (ii) a redundant row of memory cells which is associated with and selectable via a redundant row address, (b) address decoder circuitry to generate decoded row address data in response to an applied row address, (c) a memory to store decoded redundant row address data, (d) normal word line drivers, (e) redundant word line drivers, and (f) redundancy address evaluation circuitry to (i) store decoded redundant row address data which corresponds to the redundant row address, and (ii) in operation, determine whether the decoded row address data corresponds to the decoded redundant row address data, and, in response thereto, to enable the redundant word l
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: March 3, 2009
    Assignee: Innovative Silicon ISi SA
    Inventor: Anant Pratap Singh
  • Publication number: 20070297252
    Abstract: An integrated circuit device (for example, a logic device or a memory device (such as, a discrete memory device)), including a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, multiplexer circuitry, coupled to the memory cell array, wherein the multiplexer circuitry includes a plurality of data multiplexers, each data multiplexer having a plurality of inputs, including (i) a first input to receive write data which is representative of data to be written into the memory cells of the memory cell array in response to a write operation, and (ii) a second input to receive read data which is representative of data read from memory cells of the memory cell array, and an associated output to responsively output data from one of the plurality of inputs, and syndrome generation circuitry, coupled to the multiplexer circuitry, to generate: (i) a write data syndrome vector using the write data and (ii) a read data syndrome vector using the read data.
    Type: Application
    Filed: June 22, 2007
    Publication date: December 27, 2007
    Inventor: Anant Pratap Singh
  • Publication number: 20070268761
    Abstract: An integrated circuit device (for example, a logic device (such as, a microcontroller or microprocessor) or a portion of a memory device (such as, a discrete memory)), including (a) a memory cell array having a plurality of memory cells arranged in (i) a plurality of normal rows of memory cells which are associated with and selectable via normal row addresses and (ii) a redundant row of memory cells which is associated with and selectable via a redundant row address, (b) address decoder circuitry to generate decoded row address data in response to an applied row address, (c) a memory to store decoded redundant row address data, (d) normal word line drivers, (e) redundant word line drivers, and (f) redundancy address evaluation circuitry to (i) store decoded redundant row address data which corresponds to the redundant row address, and (ii) in operation, determine whether the decoded row address data corresponds to the decoded redundant row address data, and, in response thereto, to enable the redundant word l
    Type: Application
    Filed: May 17, 2007
    Publication date: November 22, 2007
    Inventor: Anant Pratap Singh