Abstract: The described technology provides a method including determining a priority level associated with a workload, determining, based on the priority level associated with the workload, a threshold cooling level of a computing unit implementing the workload, receiving, at a base motherboard controller (BMC) associated with the computing unit implementing the workload, a current temperature of the computing unit implementing the workload, and adjusting, based on the threshold cooling level of the computing unit implementing the workload and the current temperature of the computing unit implementing the workload, a usage level of a cooling system of the computing unit implementing the workload.

Abstract: Systems and methods related to efficient system on chip (SoC) power delivery with adaptive voltage headroom control are described. A method for adaptively controlling voltage headroom for a system includes, in response to either a detection of a headroom violation by a per core voltage regulator headroom monitor or a detection of a voltage droop by a per core droop detector, independently throttle operating frequency of a respective core clock signal. The method further includes, in response to meeting a predetermined criterion: (1) lowering the operating frequency of the respective core clock signal, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion, changing the voltage set point associated with the motherboard voltage regulator to a second voltage set point corresponding to a higher voltage.

Abstract: Systems and methods related to efficient system on chip (SoC) power delivery with adaptive voltage headroom control are described. A method for adaptively controlling voltage headroom for a system includes, in response to either a detection of a headroom violation by a per core voltage regulator headroom monitor or a detection of a voltage droop by a per core droop detector, independently throttle operating frequency of a respective core clock signal. The method further includes, in response to meeting a predetermined criterion: (1) lowering the operating frequency of the respective core clock signal, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion, changing the voltage set point associated with the motherboard voltage regulator to a second voltage set point corresponding to a higher voltage.

Abstract: Systems and methods related to efficient system on chip (SoC) power delivery with adaptive voltage headroom control are described. A method for adaptively controlling voltage headroom for a system includes, in response to either a detection of a headroom violation by a per core voltage regulator headroom monitor or a detection of a voltage droop by a per core droop detector, independently throttle operating frequency of a respective core clock signal. The method further includes, in response to meeting a predetermined criterion: (1) lowering the operating frequency of the respective core clock signal, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion, changing the voltage set point associated with the motherboard voltage regulator to a second voltage set point corresponding to a higher voltage.

Abstract: Systems and methods related to efficient system on chip (SoC) power delivery with adaptive voltage headroom control are described. A method for adaptively controlling voltage headroom for a system includes, in response to either a detection of a headroom violation by a per core voltage regulator headroom monitor or a detection of a voltage droop by a per core droop detector, independently throttle operating frequency of a respective core clock signal. The method further includes, in response to meeting a predetermined criterion: (1) lowering the operating frequency of the respective core clock signal, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion, changing the voltage set point associated with the motherboard voltage regulator to a second voltage set point corresponding to a higher voltage.